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latticeecp3 family data sheet preliminary ds1021 version 01.6, march 2010
www.latticesemi.com 1-1 ds1021 introduction_01.3 november 2009 preliminary data sheet ds1021 ? 2009 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. features ? higher logic density for increased system integration ? 17k to 149k luts ? 133 to 586 i/os ? embedded serdes ? 150 mbps to 3.2 gbps for generic 8b10b, 10-bit serdes, and 8-bit serdes modes ? data rates 230 mbps to 3.2 gbps per channel for all other protocols ? up to 16 channels per device: pci express, sonet/sdh, ethernet (1gbe, sgmii, xaui), cpri, smpte 3g and serial rapidio ? sysdsp? ? fully cascadable slice architecture ? 12 to 160 slices for high performance multiply and accumulate ? powerful 54-bit alu operations ? time division multiplexing mac sharing ? rounding and truncation ? each slice supports ? half 36x36, two 18x18 or four 9x9 multipliers ? advanced 18x36 mac and 18x18 multiply- ? multiply-accumulate (mmac) operations ? flexible memory resources ? up to 6.85mbits sysmem? embedded block ram (ebr) ? 36k to 303k bits distributed ram ? sysclock analog plls and dlls ? two dlls and up to ten plls per device ? pre-engineered source synchronous i/o ? ddr registers in i/o cells ? dedicated read/write levelling functionality ? dedicated gearing logic ? source synchronous standards support ? adc/dac, 7:1 lvds, xgmii ? high speed adc/dac devices ? dedicated ddr/ddr2/ddr3 memory with dqs support ? optional inter-symbol interference (isi) ? correction on outputs ? programmable sysi/o? buffer supports wide range of interfaces ? on-chip termination ? optional equalization filter on inputs ? lvttl and lvcmos 33/25/18/15/12 ? sstl 33/25/18/15 i, ii ? hstl15 i and hstl18 i, ii ? pci and differential hstl, sstl ? lvds, bus-lvds, lvpecl, rsds, mlvds ? flexible device configuration ? dedicated bank for configuration i/os ? spi boot flash interface ? dual-boot images supported ? slave spi ? transfr? i/o for simple field updates ? soft error detect embedded macro ? system level support ? ieee 1149.1 and ieee 1532 compliant ? reveal logic analyzer ? orcastra fpga configuration utility ? on-chip oscillator for initialization & general use ? 1.2v core power supply table 1-1. latticeecp3? family selection guide device ecp3-17 ecp3-35 ecp3-70 ecp3-95 ecp3-150 luts (k) 17336792149 sysmem blocks (18kbits) 38 72 240 240 372 embedded memory (kbits) 700 1327 4420 4420 6850 distributed ram bits (kbits) 36 68 145 188 303 18x18 multipliers 24 64 128 128 320 serdes (quad) 11334 plls/dlls 2 / 2 4 / 2 10 / 2 10 / 2 10 / 2 packages and serdes channels/ i/o combinations 256 ftbga (17x17 mm) 4 / 133 4 / 133 484 fpbga (23x23 mm) 4 / 22 2 4 / 295 4 / 295 4 / 295 672 fpbga (27x27 mm) 4 / 310 8 / 380 8 / 380 8 / 380 1156 fpbga (35x35 mm) 12 / 490 12 / 490 16 / 586 latticeecp3 family data sheet introduction
1-2 introduction lattice semiconductor latticee cp3 family data sheet introduction the latticeecp3? (economy plus third generation) family of fpga devices is optimized to deliver high perfor- mance features such as an enhanced dsp architecture , high speed serdes and high speed source synchronous interfaces in an economical fpga fabr ic. this combination is achieved through advances in device architecture and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications. the latticeecp3 device family expands look-up-table (lut) capacity to 149k logic elements and supports up to 486 user i/os. the latticeecp3 device family also offers up to 320 18x18 multipliers and a wide range of parallel i/o standards. the latticeecp3 fpga fabric is optimized with high performance and low cost in mind. the latticeecp3 devices utilize reconfigurable sram lo gic technology and provide po pular building blocks such as lut-based logic, distrib- uted and embedded memory, phase locked loops (plls), delay locked loops (dlls), pre-engineered source synchronous i/o support, enhanced sysdsp slices and advanced configuration support, including encryption and dual-boot capabilities. the pre-engineered source synchronous logic implemented in the latticeecp3 device family supports a broad range of interface standards, including ddr3, xgmii and 7:1 lvds. the latticeecp3 device family also features high speed serdes with dedicated pcs functions. high jitter toler- ance and low transmit jitter allow the serdes plus pcs blocks to be configured to support an array of popular data protocols including pci express, smpte, ethernet (xaui, gbe, and sgmii) and cpri. transmit pre-empha- sis and receive equalization settings make the serdes suitable for transmission and reception over various forms of media. the latticeecp3 devices also provide fl exible, reliable and secure configuration options, such as dual-boot capa- bility, bit-stream encryption, a nd transfr field upgrade features. the isplever ? design tool suite from lattice allows large comp lex designs to be efficiently implemented using the latticeecp3 fpga family. synthesis library support for latt iceecp3 is available for popular logic synthesis tools. the isplever tool uses the synthesis tool output along with the constr aints from its floor pl anning tools to place and route the design in the latticeecp3 device. the isplever tool ex tracts the timing from the routing and back- annotates it into the design for timing verification. lattice provides many pre-engineered ip (intellectual property) isplevercore? modules for the latticeecp3 family. by using these configurable soft core ips as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity.
www.latticesemi.com 2-1 ds1021 architecture_01.5 march 2010 preliminary data sheet ds1021 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. architecture overview each latticeecp3 device contains an array of logic blocks surrounded by programmable i/o cells (pic). inter- spersed between the rows of logic blocks are rows of sysmem? embedded block ram (ebr) and rows of sys- dsp? digital signal processing slices, as shown in figu re 2-1. in addition, the latticeecp3 family contains serdes quads on the bottom of the device. there are two kinds of logic blocks, the programmable functional unit (pfu) and programmable functional unit without ram (pff). the pfu contains the building blocks for logic, arithmetic, ram and rom functions. the pff block contains building blocks for logic, arithmetic and rom functions. both pfu and pff blocks are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. logic blocks are arranged in a two- dimensional array. only one type of block is used per row. the latticeecp3 devices contain one or more rows of sysmem ebr blocks. sysmem ebrs are large, dedicated 18kbit fast memory blocks. each sysmem block can be configured in a variety of depths and widths as ram or rom. in addition, latticeecp3 devices contain up to two rows of dsp slices. each dsp slice has multipliers and adder/accumulators, whic h are the building blocks for comple x signal processing capabilities. the latticeecp3 devices feature up to 16 embedded 3.2gbps serdes (serializer / deserializer) channels. each serdes channel contains independent 8b/10b encoding / deco ding, polarity adjust and elastic buffer logic. each group of four serdes channels, along with its physical coding sub-layer (pcs) block, creates a quad. the func- tionality of the serdes/pcs quads can be controlled by memo ry cells set during device configuration or by regis- ters that are addressable during device operation. the registers in every quad can be programmed via the serdes client interface (sci). these quads (up to four) are located at the bottom of the devices. each pic block encompasses two pios (pio pairs) with t heir respective sysi/o buffers. the sysi/o buffers of the latticeecp3 devices are arranged in seven banks, allowing the implementation of a wide variety of i/o standards. in addition, a separate i/o bank is provided for the programming interfaces. 50% of the pio pairs on the left and right edges of the device can be configured as lvds trans mit/receive pairs. the pic logic also includes pre-engi- neered support to aid in the implementation of high speed source synchronous standards such as xgmii, 7:1 lvds, along with memory interfaces including ddr3. other blocks provided include plls, dlls and configuratio n functions. the latticeecp3 architecture provides two delay locked loops (dlls) and up to ten phase locked loo ps (plls). in addition, each latticeecp3 family mem- ber provides two dlls per device. the pll and dll blocks are located at the end of the ebr/dsp rows. the configuration block that supports features such as configuration bit-stream decryption, transparent updates and dual-boot support is located toward the center of this ebr row. every device in the latticeecp3 family sup- ports a sysconfig? port located in the corner between banks one and two, which allows for serial or parallel device configuration. in addition, every device in the family has a jtag port. this family also provides an on -chip oscillator and soft error detect capability. the la tticeecp3 devices use 1.2v as their core voltage. latticeecp3 family data sheet architecture
2-2 architecture lattice semiconductor latticee cp3 family data sheet figure 2-1. simplified block diagram, latticeecp3-35 device (top level) pfu blocks the core of the latticeecp3 device consists of pfu blocks, which are provided in two forms, the pfu and pff. the pfus can be programmed to perform logic, arithmetic, distributed ram and distributed rom functions. pff blocks can be programmed to perform logic, arithmetic and rom functions. except where necessary, the remain- der of this data sheet will use the term pfu to refer to both pfu and pff blocks. each pfu block consists of four interconnected slices nu mbered 0-3 as shown in figure 2-2. each slice contains two luts. all the interconnections to and from pfu blocks are from routing. there are 50 inputs and 23 outputs associated with each pfu block. serdes/pcs ch 3 serdes/pcs ch 2 serdes/pcs ch 1 serdes/pcs ch 0 sysio bank 7 sysio bank 2 sysio bank 0 sysio bank 1 sysio bank 3 sysio bank 6 configuration logic: dual-boot, encryption and transparent updates on-chip oscillator pre-engineered source synchronous support: ddr3 - 800mbps generic - up to 1gbps flexible routing: optimized for speed and routability flexible sysio: lvcmos, hstl, sstl, lvds up to 486 i/os programmable function units: up to 149k luts sysclock plls & dlls: frequency synthesis and clock alignment enhanced dsp slices: multiply, accumulate and alu jtag sysmem block ram: 18kbit 3.2gbps serdes note: there is no bank 4 or bank 5 in latticeecp3 devices.
2-3 architecture lattice semiconductor latticee cp3 family data sheet figure 2-2. pfu diagram slice slice 0 through slice 2 contain two lut4s feeding two re gisters, whereas slice 3 contains two lut4s only. for pfus, slice 0 through slice 2 can be configured as dist ributed memory, a capability not available in the pff. table 2-1 shows the capability of the slices in both pff and pfu blocks along with the operation modes they enable. in addition, each pfu contains logic that allows the luts to be combined to perform functions such as lut5, lut6, lut7 and lut8. there is control logic to pe rform set/reset functions (programmable as synchronous/ asynchronous), clock select, chip-select and wider ram/rom functions. table 2-1. resources and modes available per slice figure 2-3 shows an overview of the internal logic of the slice. the registers in the slice can be configured for posi- tive/negative and edge triggered or level sensitive clocks. slices 0, 1 and 2 have 14 input signals: 13 signals fr om routing and one from the carry-chain (from the adjacent slice or pfu). there are seven outputs: six to routing and one to carry-chain (to the adjacent pfu). slice 3 has 10 input signals from routing and four signals to routing. tabl e 2-2 lists the signals associated with slice 0 to slice 2. slice pfu block pff block resources modes resources modes slice 0 2 lut4s and 2 registers logic, ripple, ram, rom 2 lut4s and 2 registers logic, ripple, rom slice 1 2 lut4s and 2 registers logic, ripple, ram, rom 2 lut4s and 2 registers logic, ripple, rom slice 2 2 lut4s and 2 registers logic, ripple, ram, rom 2 lut4s and 2 registers logic, ripple, rom slice 3 2 lut4s logic, rom 2 lut4s logic, rom slice 0 lut4 & carry lut4 & carry d d slice 1 lut4 & carry lut4 & carry slice 2 lut4 & carry lut4 & carry from routing to routing slice 3 lut4 lut4 d d d d ff ff ff ff ff ff
2-4 architecture lattice semiconductor latticee cp3 family data sheet figure 2-3. slice diagram table 2-2. slice signal descriptions function type signal names description input data signal a0, b0, c0, d0 inputs to lut4 input data signal a1, b1, c1, d1 inputs to lut4 input multi-purpose m0 multipurpose input input multi-purpose m1 multipurpose input input control signal ce clock enable input control signal lsr local set/reset input control signal clk system clock input inter-pfu signal fc fast carry-in 1 input inter-slice signal fxa intermediate signal to generate lut6 and lut7 input inter-slice signal fxb intermediate signal to generate lut6 and lut7 output data signals f0, f1 lut4 output register bypass signals output data signals q0, q1 register outputs output data signals ofx0 output of a lut5 mux output data signals ofx1 output of a lut6, lut7, lut8 2 mux depending on the slice output inter-pfu signal fco slice 2 of each pfu is the fast carry chain output 1 1. see figure 2-3 for connection details. 2. requires two pfus. lut4 & carry* slice ff* ofx0 f0 q0 ci co lut4 & carry* ci co ff* ofx1 f1 q1 f/sum f/sum d d fci from different slice/pfu fco to different slice/pfu lut5 mux from routing to routing for slices 0 and 1, memory control signals are generated from slice 2 as follows: wck is clk wre is from lsr di[3:2] for slice 1 and di[1:0] for slic e 0 data from slice 2 wad [a:d] is a 4-bit address from slice 2 lut input * not in slice 3 a0 c0 d0 a1 b1 c1 d1 ce clk lsr m1 m0 fxb fxa b0
2-5 architecture lattice semiconductor latticee cp3 family data sheet modes of operation each slice has up to four potential modes of operation: logic, ripple, ram and rom. logic mode in this mode, the luts in each slice are configured as 4-input combinatorial lookup tables. a lut4 can have 16 possible input combinations. any four input logic functions can be generated by programming this lookup table. since there are two lut4s per slice, a lut5 can be cons tructed within one slice. larger look-up tables such as lut6, lut7 and lut8 can be constructed by concatenatin g other slices. note lut8 requires more than four slices. ripple mode ripple mode supports the efficient implementation of small arithmetic functions. in ripple mode, the following func- tions can be implemented by each slice: ? addition 2-bit ? subtraction 2-bit ? add/subtract 2-bit using dynamic control ? up counter 2-bit ? down counter 2-bit ? up/down counter with asynchronous clear ? up/down counter with preload (sync) ? ripple mode multiplier building block ? multiplier support ? comparator functions of a and b inputs ? a greater-than-or-equal-to b ? a not-equal-to b ? a less-than-or-equal-to b ripple mode includes an optional configuration that performs arithmetic using fast carry chain methods. in this con- figuration (also referred to as ccu2 mode) two additional signals, carry generate and carry propagate, are gener- ated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating slices. ram mode in this mode, a 16x4-bit distributed single port ram (spr ) can be constructed using each lut block in slice 0 and slice 1 as a 16x1-bit memory. slice 2 is used to provid e memory address and control signals. a 16x2-bit pseudo dual port ram (pdpr) memory is created by using one s lice as the read-write port and the other companion slice as the read-only port. latticeecp3 devices support distributed memory initialization. the lattice design tools support the creation of a variety of different size memories. where appropriate, the soft- ware will construct these using distribute d memory primitives that represent th e capabilities of the pfu. table 2-3 shows the number of slices required to implement different distributed ram primitives. for more information about using ram in latticeecp3 devices, please see tn1179, latticeecp3 memory usage guide . table 2-3. number of slices required to implement distributed ram spr 16x4 pdpr 16x4 number of slices 3 3 note: spr = single port ram, pdpr = pseudo dual port ram
2-6 architecture lattice semiconductor latticee cp3 family data sheet rom mode rom mode uses the lut logic; hence, slices 0 through 3 can be used in rom mode. preloading is accomplished through the programming interface during pfu configuration. for more information, please refer to tn1179, latticeecp3 memory usage guide . routing there are many resources provided in the latticeecp3 devices to route signals individually or as busses with related control signals. the routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. the latticeecp3 family has an enhanc ed routing architecture that produces a compact design. the isplever design tool suite takes the output of the synthesis tool and places and routes the design. sysclock plls and dlls the sysclock plls provide the ability to synthesize clock frequencies. all the devices in the latticeecp3 family support four to ten full-featured general purpose plls. general purpose pll the architecture of the pll is shown in figure 2-4. a description of the pll functionality follows. clki is the reference frequency (generated either from the pin or from routing) for the pll. clki feeds into the input clock divider block. the clkfb is the feedback signal (generated from clkop, clkos or from a user clock pin/logic). this signal feeds into the feedback divider. th e feedback divider is used to multiply the reference fre- quency. both the input path and feed back signals enter the volta ge controlled oscillator (vco) bl ock. in this block the dif- ference between the input path and feedback signals is used to control the frequency an d phase of the oscillator. a lock signal is generated by the vco to indicate that the vco has locked onto the input clock signal. in dynamic mode, the pll may lose lock after a dynamic delay adjustment and not relock until the t lock parameter has been satisfied. the output of the vco then enters the clkop divider. the clkop divider allows the vco to operate at higher fre- quencies than the clock output (clkop), thereby increasing the frequency range. the phase/duty select block adjusts the phase and duty cycle of the clkos signal. the phase/duty cycle setting can be pre-programmed or dynamically adjusted. a secondary divider takes the clkop or clkos signal and uses it to derive lower frequency outputs (clkok). the primary output from the clkop divider (clkop) along with the outputs from the secondary dividers (clkok and clkok2) and phase/duty select (clkos) are fed to the clock distribution network. the pll allows two methods for adjusting the phase of sign al. the first is referred to as fine delay adjustment. this inserts up to 16 nominal 125ps delays to be applied to the secondary pll output. the number of steps may be set statically or from the fpga logic. the second method is referred to as coarse phase adjustment. this allows the phase of the rising and falling edge of the secondary pll output to be adjusted in 22.5 degree steps. the number of steps may be set statically or from the fpga logic.
2-7 architecture lattice semiconductor latticee cp3 family data sheet figure 2-4. general purpose pll diagram table 2-4 provides a description of the signals in the pll blocks. table 2-4. pll blocks signal descriptions delay locked loops (dll) in addition to plls, the latticeecp3 family of devices has two dlls per device. clki is the input frequency (generated either from the pin or routing) for the dll. clki feeds into the output muxes block to bypass the dll, directly to the delay chain block and (directly or through divider circuit) to the reference input of the phase detector (pd) input mux. the reference signal for the pd can also be generated from the delay chain signals. the feedback input to the pd is generated from the clkfb pin or from a tapped signal from the delay chain. the pd produces a binary number proportional to the phase and frequency difference between the reference and feedback signals. based on these inputs, the alu determines the correct digital control codes to send to the delay signal i/o description clki i clock input from external pin or routing clkfb i pll feedback input from clkop, clkos, or from a user clock (pin or logic) rst i ?1? to reset pll counters, vco, charge pumps and m-dividers rstk i ?1? to reset k-divider wrdel i dpa fine delay adjust input clkos o pll output to clock tree ( phase shifted/duty cycle changed) clkop o pll output to cloc k tree (no phase shift) clkok o pll output to clock tree through secondary clock divider clkok2 o pll output to clock tree (clkop divided by 3) lock o ?1? indicates pll lock to clki fda [3:0] i dynamic fine delay adjustment on clkos output drpai[3:0] i dynamic coarse phase shift, rising edge setting dfpai[3:0] i dynamic coarse phase shift, falling edge setting clkfb divider rst clkfb clki lock clkop clkos rstk wrdel fda[3:0] clkok2 clkok clki divider pfd vco/ loop filter clkop divider phase/ duty cycle/ duty trim duty trim clkok divider lock detect 3 drpai[3:0] dfpai[3:0]
2-8 architecture lattice semiconductor latticee cp3 family data sheet chain in order to better match the reference and feedback signals. this digital code from the alu is also transmit- ted via the digital control bus (dcntl) bus to its associated slave delay lines (two per dll). the aluhold input allows the user to suspend the alu ou tput at its current value. the uddcntl signal allows the user to latch the current value on the dcntl bus. the dll has two clock outputs, clkop and clkos. these outputs can individually select one of the outputs from the tapped delay line. the clkos has optional fine delay shift and divider blocks to allow this output to be further modified, if required. the fine delay shift block allows the clkos output to phase shifted a further 45, 22.5 or 11.25 degrees relative to its normal position. both the clkos and clkop outputs are available with optional duty cycle correction. divide by two and divide by four frequencies are available at clkos. the lock output signal is asserted when the dll is locked. figure 2-5 shows the dll block diagram and table 2-5 provides a description of the dll inputs and outputs. the user can configure the dll for many common functions such as time reference delay mode and clock injection removal mode. lattice provides primitives in its design tools for these functions. figure 2-5. delay locked loop diagram (dll) clkop clkos lock clkfb clki aluhold dcntl[5:0]* grayo[5:0] inco uddcntl phase detector delay3 delay2 delay1 delay0 delay4 reference feedback 6 4 2 4 2 rstn (from routing or external pin) from clkop (dll internal), from clock net (clkop) or from a user clock (pin or logic) arithmetic logic unit lock detect digital control output delay chain output muxes duty cycle 50% duty cycle 50% inci grayi[5:0] diff * this signal is not user accessible. this can only be used to feed the slave delay line.
2-9 architecture lattice semiconductor latticee cp3 family data sheet table 2-5. dll signals latticeecp3 devices have two general dlls and four slave delay lines, two per dll. the dlls are in the lowest ebr row and located adjacent to the ebr. each dll replaces one ebr block. one slave delay line is placed adja- cent to the dll and the duplicate slave delay line (in figu re 2-6) for the dll is placed in the i/o ring between banks 6 and 7 and banks 2 and 3. the outputs from the dll and slave delay lines are fed to the clock distribution network. for more information, please see tn1178, latticeecp3 sysclock pll/dll design and usage guide . figure 2-6. top-level block diagram, high-speed dll and slave delay line signal i/o description clki i clock input from external pin or routing clkfb i dll feed input from dll output, clock net, routing or external pin rstn i active low synchronous reset aluhold i active high freezes the alu uddcntl i synchronous enable signal (hold high for two cycles) from routing clkop o the primary clock output clkos o the secondary clock output with fine de lay shift and/or division by 2 or by 4 lock o active high phase lock indicator inci i incremental indicator from another dll via cib. grayi[5:0] i gray-coded digital control bus from another dll in time reference mode. diff o difference indicator when dcntl is differen ce than the internal setting and update is needed. inco o incremental indicator to other dlls via cib. grayo[5:0] o gray-coded digital control bus to other dlls via cib clkop clkos lock gray_out[5:0] inc_out diff dcntl[5:0]* clko (to edge clock muxes as clkindel) slave delay line latticeecp3 high-speed dll dcntl[5:0] clki hold gray_in[5:0] inc_in rstn gsrn uddcntl dcps[5:0] tpio0 (l) or tpio1 (r) gpll_pio cib (data) cib (clk) gdll_pio top eclk1 (l) or top eclk2 (r) fb cib (clk) internal from clkop gdllfb_pio eclk1 clkfb clki 4 3 2 1 0 4 3 2 1 0 4 3 2 1 0 * this signal is not user accessible. it can only be used to feed the slave delay line.
2-10 architecture lattice semiconductor latticee cp3 family data sheet pll/dll cascading latticeecp3 devices have been designed to allow certain combinations of pll and dll cascading. the allowable combinations are: ? pll to pll supported ? pll to dll supported the dlls in the latticeecp3 are used to shift the clock in relation to the data for source synchronous inputs. plls are used for frequency synthesis and clock generation fo r source synchronous interfaces. cascading pll and dll blocks allows applications to utilize the unique benefits of bo th dlls and plls. for further information about the dll, please see the list of technical documentation at the end of this data sheet. pll/dll pio input pin connections all latticeecp3 devices contains two dlls and up to ten plls, arranged in quadrants. if a pll and a dll are next to each other, they share input pins as shown in the figure 2-7. figure 2-7. sharing of pio pins by plls and dlls in latticeecp3 devices clock dividers latticeecp3 devices have two clock dividers, one on the left side and one on the right side of the device. these are intended to generate a slower-speed system clock from a high-speed edge clock. the block operates in a 2, 4 or 8 mode and maintains a known phase relationship between the divided down clock and the high-speed clock based on the release of its reset signal. the clock divider s can be fed from selected pll/dll outputs, the slave delay lines, routing or from an external clock input. the clock divider outputs serve as primary clock sources and feed into the clock distribution network. the reset (rst) control signal resets input and asynchronously forces all outputs to low. the release si gnal releases outputs synchr onously to the input clock. for further information on clock dividers, please see tn1178, latticeecp3 sysclock pll/dl l design and usage guide . figure 2-8 shows the clock divider connections. pll dll dll_pio pll_pio note: not every pll has an associated dll.
2-11 architecture lattice semiconductor latticee cp3 family data sheet figure 2-8. clock divider connections clock distribution network latticeecp3 devices have eight quadrant-based primary clocks and eight secondary clock/control sources. two high performance edge clocks are available on the top, left, and right edges of the device to support high speed interfaces. these clock sources are selected from external i/os, the sysclock plls, dlls or routing. these clock sources are fed throughout the chip via a clock distribution system. primary clock sources latticeecp3 devices derive clocks from six primary source types: pll outputs, dll outputs, clkdiv outputs, ded- icated clock inputs, routing and serdes quads. latticee cp3 devices have two to ten sysclock plls and two dlls, located on the left and right sides of the device. there are six dedicated clock inputs: two on the top side, two on the left side and two on the right side of the device. figures 2-9, 2-10 and 2-11 show the primary clock sources for latticeecp3 devices. figure 2-9. primary clock sources for latticeecp3-17 rst release 1 2 4 8 eclk2 clkop (pll) clkop (dll) eclk1 clkdiv primary clock sources to eight quadrant clock selection from routing from routing pll dll pll input note: clock inputs can be configured in differential or single-ended mode. dll input clk div serdes quad clock input clock input pll input dll input clock input clock input clock input clock input pll dll clk div
2-12 architecture lattice semiconductor latticee cp3 family data sheet figure 2-10. primary clock sources for latticeecp3-35 figure 2-11. primary clock sources for latticeecp3-70, -95, -150 primary clock sources to eight quadrant clock selection from routing from routing pll pll dll pll input pll input dll input clk div clock input clock input pll input pll input dll input clock input clock input clock input clock input pll pll dll clk div serdes quad note: clock inputs can be configured in differential or single-ended mode. primary clock sources to eight quadrant clock selection from routing from routing pll pll dll pll input pll input dll input clk div clock input clock input pll input pll input dll input clock input clock input clock input clock input pll pll pll input pll input pll pll pll pll input pll input pll pll pll input pll input pll dll clk div serdes quad serdes quad serdes quad serdes quad (ecp3-150 only) note: clock inputs can be configured in differential or single-ended mode.
2-13 architecture lattice semiconductor latticee cp3 family data sheet primary clock routing the purpose of the primary clock routing is to distribute primary clock sources to the destination quadrants of the device. a global primary clock is a primary clock that is distributed to all quadrants. the clock routing structure in latticeecp3 devices consists of a network of eight primary clock lines (clk0 through clk7) per quadrant. the pri- mary clocks of each quadrant are generated from muxes located in the center of the device. all the clock sources are connected to these muxes. figure 2-12 shows the clock routing for one quadrant. each quadrant mux is identi- cal. if desired, any clock can be routed globally. figure 2-12. per quadrant primary clock selection dynamic clock control (dcc) the dcc (quadrant clock enable/disable) feature allows internal logic control of the quadrant primary clock net- work. when a clock network is disabled, all the logic fed by that clock does not toggle, reducing the overall power consumption of the device. dynamic clock select (dcs) the dcs is a smart multiplexer function available in the primary clock routing. it switches between two independent input clock sources without any glitches or runt pulses. this is achieved regardless of when the select signal is tog- gled. there are two dcs blocks per quadrant; in total, there are eight dcs blocks per device. the inputs to the dcs block come from the center muxes. the output of the dcs is connected to primary clocks clk6 and clk7 (see figure 2-12). figure 2-13 shows the timing waveforms of the default dcs operating mode. the dcs block can be programmed to other modes. for more information about the dcs, please see the list of technical documentation at the end of this data sheet. figure 2-13. dcs waveforms clk0 clk1 clk2 clk3 clk4 clk5 clk6 clk7 63:1 63:1 63:1 63:1 58:1 58:1 58:1 58:1 63:1 63:1 dcc dcc dcc dcc dcs dcs dcc dcc 8 primary clocks (clk0 to clk7) per quadrant plls + dlls + clkdivs + pclk pios + serdes quads clk0 sel dcsout clk1
2-14 architecture lattice semiconductor latticee cp3 family data sheet secondary clock/control sources latticeecp3 devices derive eight secondary clock sources (sc0 through sc7) from six dedicated clock input pads and the rest from routing. figure 2-14 shows the secondary clock sources. all eight secondary clock sources are defined as inputs to a per-region mux sc0-sc7. sc0-sc 3 are primary for control signals (ce and/or lsr), and sc4-sc7 are for clock and high fanout data. in an actual implementation, there is some overlap to maximize routability. in addi tion to sc0-sc3, sc7 is also an input to the control signals (lsr or ce). sc0-sc2 are also inputs to clocks along with sc4-sc7. high fanout logic signals (lut inputs) will utilize the x2 and x0 switches where sc0-sc7 are inputs to x2 switches, and sc4-sc7 are inputs to x0 switches. note that through x0 swit ches, sc4-sc7 can also acce ss control signals ce/lsr. figure 2-14. secondary clock sources secondary clock/control routing global secondary clock is a secondary clock that is distributed to all regions. the purpose of the secondary clock routing is to distribute the second ary clock sources to the secondary clock regions. secondary clocks in the latticeecp3 devices are region-based resources. certain ebr rows and special vertical routing channels bind the secondary clock regions. this special vertical routing channel aligns with either the left edge of the center dsp slice in the dsp row or the center of the dsp row. figure 2-15 shows this special vertical routing channel and the 20 secondary clock regions for the latticeecp3 family of de vices. all devices in the latticeecp3 family have eight secondary clock sources from routing from routing from routing from routing from routing from routing from routing from routing from routing from routing clock input clock input clock input clock input from routing from routing note: clock inputs can be configured in differential or single-ended mode. from routing from routing clock input clock input from routing from routing
2-15 architecture lattice semiconductor latticee cp3 family data sheet secondary clock resources per region (sc0 to sc7). the same secondary clock routing can be used for control signals. table 2-6. secondary clock regions figure 2-15. latticeecp3-70 and latticeecp3-95 secondary clock regions device number of secondary clock regions ecp3-17 16 ecp3-35 16 ecp3-70 20 ecp3-95 20 ecp3-150 36 sysio bank 0 sysio bank 1 serdes sysio bank 7 sysio bank 2 sysio bank 6 sysio bank 3 configuration bank secondary clock region r1c1 secondary clock region r2c1 secondary clock region r3c1 secondary clock region r4c1 secondary clock region r5c1 secondary clock region r1c2 secondary clock region r2c2 secondary clock region r3c2 secondary clock region r4c2 secondary clock region r5c2 secondary clock region r1c3 vertical routing channel regional boundary secondary clock region r2c3 secondary clock region r3c3 secondary clock region r4c3 secondary clock region r5c3 secondary clock region r1c4 secondary clock region r2c4 secondary clock region r3c4 secondary clock region r4c4 secondary clock region r5c4 ebr row regional boundary ebr row regional boundary spine repeaters
2-16 architecture lattice semiconductor latticee cp3 family data sheet figure 2-16. per region secondary clock selection slice clock selection figure 2-17 shows the clock selections and figure 2-18 shows the control selections for slice0 through slice2. all the primary clocks and seven secondary clocks are routed to this clock selection mux. other signals can be used as a clock input to the slices via routing. slice controls are generated from the secondary clocks/controls or other signals connected via routing. if none of the signals are selected for both clock and control then the default value of the mux output is 1. slice 3 does not have any registers; therefore it does not have the clock or control muxes. figure 2-17. slice0 through slice2 clock selection figure 2-18. slice0 through slice2 control selection sc0 sc1 sc2 sc3 sc4 sc5 8:1 8:1 8:1 8:1 sc6 8:1 sc7 8:1 8:1 8:1 8 secondary clocks (sc0 to sc7) per region clock/control secondary clock feedlines: 8 pios + 16 routing clock to slice primary clock secondary clock routing vcc 8 7 12 1 28:1 slice control secondary control routing vcc 5 14 1 20:1
2-17 architecture lattice semiconductor latticee cp3 family data sheet edge clock sources edge clock resources can be driven from a variety of sources at the same edge. edge clock resources can be driven from adjacent edge clock pios, primary clock pios, plls, dlls, slave delay and clock dividers as shown in figure 2-19. figure 2-19. edge clock sources edge clock routing latticeecp3 devices have a number of high-speed edge clocks that are intended for use with the pios in the implementation of high-speed interfaces. there are six edge clocks per device: two edge clocks on each of the top, left, and right edges. different pll and dll outputs are routed to the two muxes on the left and right sides of the device. in addition, the clkindel signal (generated from the dll slave delay line block) is routed to all the edge clock muxes on the left and right sides of the device. figure 2-20 shows the selection muxes for these clocks. six edge clocks (eclk) two clocks per edge sources for right edge clocks clock input clock input from routing from routing from routing clock input clock input from routing from routing clock input clock input from routing sources for left edge clocks notes: 1. clock inputs can be configured in differential or single ended mode. 2. the two dlls can also drive the two top edge clocks. 3. the top left and top right pll can also drive the two top edge clocks. sources for top edge clocks dll input pll input dll input pll input slave delay dll pll dll pll slave delay
2-18 architecture lattice semiconductor latticee cp3 family data sheet figure 2-20. sources of edge clock (left and right edges) figure 2-21. sources of edge clock (top edge) the edge clocks have low injection delay and low skew. they are used to clock the i/o registers and thus are ideal for creating i/o interfaces with a single clock signal an d a wide data bus. they are also used for ddr memory or generic ddr interfaces. left and right edge clocks eclk1 routing input pad pll input pad dll output clkop pll output clkop clkindel from dll slave delay left and right edge clocks eclk2 routing input pad pll input pad dll output clkos pll output clkos clkindel from dll slave delay 6:1 6:1 eclk1 eclk2 input pad top left pll_clkop routing clkindel top right pll_clkos left dll_clkop right dll_clkos (left dll_del) input pad top right pll_clkop routing clkindel top left pll_clkos right dll_clkop left dll_clkos (right dll_del) 7:1 7:1
2-19 architecture lattice semiconductor latticee cp3 family data sheet the edge clocks on the top, left, and right sides of the device can drive the secondary clocks or general routing resources of the device. the left and right side edge clocks also can drive the primary clock network through the clock dividers (clkdiv). sysmem memory latticeecp3 devices contain a number of sysmem embed ded block ram (ebr). the ebr consists of an 18-kbit ram with memory core, dedicated input registers and output registers with separate clock and clock enable. each ebr includes functionality to support true dual-port, pseudo dual-port, single-port ram, rom and fifo buffers (via external pfus). sysmem memory block the sysmem block can implement single port, dual port or pseudo dual port memories. each block can be used in a variety of depths and widths as shown in table 2-7. fifos can be implemented in sysmem ebr blocks by imple- menting support logic with pfus . the ebr block facilitates pa rity checking by supporting an optional parity bit for each data byte. ebr blocks provide byte-enable support for configurations with18-bit and 36-bit data widths. for more information, please see tn1179, latticeecp3 memory usage guide . table 2-7. sysmem block configurations bus size matching all of the multi-port memory modes support different widths on each of the ports. the ram bits are mapped lsb word 0 to msb word 0, lsb word 1 to msb word 1, and so on. although the word size and number of words for each port varies, this mapping scheme applies to each port. ram initialization and rom operation if desired, the contents of the ram can be pre-loaded duri ng device configuration. by preloading the ram block during the chip configuration cycle and disabling the write controls, the sysmem block can also be utilized as a rom. memory cascading larger and deeper blocks of ram can be created using ebr sysmem blocks. typically, the lattice design tools cascade memory transparently, bas ed on specific design inputs. memory mode configurations single port 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36 true dual port 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 pseudo dual port 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36
2-20 architecture lattice semiconductor latticee cp3 family data sheet single, dual and pseudo-dual port modes in all the sysmem ram modes the input data and address for the ports are registered at the input of the memory array. the output data of the memory is optionally registered at the output. ebr memory supports the following forms of write behavior for single port or dual port operation: 1. normal ? data on the output appe ars only during a read cycle. during a write cycle, the data (at the current address) does not appear on the output. this mode is supported for all data widths. 2. write through ? a copy of the input data appears at the output of the same port during a write cycle. this mode is supported for all data widths. 3. read-before-write (ea devices only) ? when new data is written, the old content of the address appears at the output. this mode is supported for x9, x18, and x36 data widths. memory core reset the memory array in the ebr utilizes la tches at the a and b out put ports. these latches can be reset asynchro- nously or synchronously. rsta and rstb are local signal s, which reset the output latches associated with port a and port b, respectively. the global reset (gsrn) signal can reset both ports. the output data latches and asso- ciated resets for both ports are as shown in figure 2-22. figure 2-22. memory core reset for further information on the sysmem ebr block, please se e the list of technical documentation at the end of this data sheet. sysdsp? slice the latticeecp3 family provides an enhanced sysdsp archit ecture, making it ideally su ited for low-cost, high-per- formance digital signal processing (dsp) applications. ty pical functions used in these applications are finite impulse response (fir) filters, fast fourier transforms (fft) functions, correlators, reed-solomon/turbo/convo- lution encoders and decoders. these complex signal proc essing functions use similar building blocks such as mul- tiply-adders and multiply-accumulators. sysdsp slice approach co mpared to general dsp conventional general-purpose dsp chips typically contain one to four (multiply and accumulate) mac units with fixed data-width multipliers; this leads to limited parallelism and limited throughput. their throughput is increased by higher clock speeds. the latticeecp3, on the other hand, ha s many dsp slices that support different data widths. q set d l clr output data latches memory core port a[17:0] q set d port b[17:0] rstb gsrn programmable disable rsta l clr
2-21 architecture lattice semiconductor latticee cp3 family data sheet this allows designers to use highly parallel implementations of dsp functions. designers can optimize dsp perfor- mance vs. area by choosing appropriate levels of parallelism. figure 2-23 compares the fully serial implementation to the mixed parallel and serial implementation. figure 2-23. comparison of general dsp and latticeecp3 approaches latticeecp3 sysdsp slice architecture features the latticeecp3 sysdsp slice has been significantly e nhanced to provide functions needed for advanced pro- cessing applications. these enha ncements provide improved flex ibility and resource utilization. the latticeecp3 sysdsp slice supports ma ny functions that include the following: ? multiply (one 18x36, two 18x18 or four 9x9 multiplies per slice) ? multiply (36x36 by cascading across two sysdsp slices) ? multiply accumulate (up to 18x36 multipliers feeding an accumulator that can have up to 54-bit resolution) ? two multiplies feeding one accumulate per cycle for increased processing with lower latency (two 18x18 mul- tiplies feed into an accumulator that can accumulate up to 52 bits) ? flexible saturation and rounding options to satisfy a diverse set of applications situations ? flexible cascading across dsp slices ? minimizes fabric use for common dsp and alu functions ? enables implementation of fir filter or similar structures using dedicated sysdsp slice resources only ? provides matching pipeline registers ? can be configured to continue cascading from one row of sysdsp slices to another for longer cascade chains ? flexible and powerful arithmetic logic unit (alu) supports: ? dynamically selectable alu opcode ? ternary arithmetic (addition/subtraction of three inputs) ? bit-wise two-input logic operations (and, or, nand, nor, xor and xnor) ? eight flexible and programmable alu flags that can be used for multiple pattern detection scenarios, such multiplier 0 multiplier 1 x x x multiplier k (k adds) output single multiplier x operand a operand a operand b operand b operand b operand a operand a operand b accumulator m loops function implemented in general purpose dsp function implemented in latticeecp3 m/k accumulate m/k loops + +
2-22 architecture lattice semiconductor latticee cp3 family data sheet as, overflow, underflow and convergent rounding, etc. ? flexible cascading across slices to get larger functions ? rtl synthesis friendly synchronous re set on all registers, wh ile still supporting asynch ronous reset for legacy users ? dynamic mux selection to allow time division multiplexi ng (tdm) of resources for applications that require processor-like flexibility that enables di fferent functions for each clock cycle for most cases, as shown in figure 2-24, the latticeecp3 dsp slice is backwards-compatible with the latticeecp2? sysdsp block, such that, legacy applications can be targeted to the latticeecp3 sysdsp slice. the functionality of one latticeecp2 sysdsp block can be ma pped into two adjacent latticeecp3 sysdsp slices, as shown in figure 2-25. figure 2-24. simplified sysdsp slice block diagram pr ir ir ir ir ir ir pr pr multa multa multb multb mult18-0 mult18-0 mult18-1 one of these mult18-1 or or input registers from sro of left-side dsp alu op-codes slice 0 slice 1 cascade from left dsp accumulator/alu (54) accumulator/alu (54) to fpga core from fpga core cascade to right dsp intermediate pipeline registers output registers or or or or or or carry out reg. carry out reg. 9x9 9x9 9x9 9x9 9x9 9x9 9x9 9x9 casc a0 casc a1 ir ir pr
2-23 architecture lattice semiconductor latticee cp3 family data sheet figure 2-25. detailed sysdsp slice diagram the latticeecp2 sysdsp block supports the following basic elements. ? mult (multiply) ? mac (multiply, accumulate) ? multaddsub (multiply, addition/subtraction) ? multaddsubsum (multiply, addition/subtraction, summation) table 2-8 shows the capabilities of each of the latticeecp3 slic es versus the above functions. table 2-8. maximum number of elements in a slice some options are available in the four elements. the input register in all the elements can be directly loaded or can be loaded as a shift register from previous operand registers. by selecting ?dynamic operation? the following opera- tions are possible: ? in the add/sub option the accumulator can be switched between addition and subtraction on every cycle. ? the loading of operands can switch between parallel and serial operations. width of multiply x9 x18 x36 mult 4 2 1/2 mac 1 1 ? multaddsub 2 1 ? multaddsubsum 1 1 1/2 ? 1. one slice can implement 1/2 9x9 m9x9addsubs um and two m9x9addsubsum with two slices. r= a b c r = logic (b, c) aa ab ba bb multa multb bmux amux cmux alu a_alu b_alu ir pr pr or rounding a_alu opcode c cin cout srob sroa srib sria c_alu 0 00 from fpga core to fpga core ir = input register pr = pipeline register or = output register fr = flag register note: a_alu, b_alu and c_alu are internal signals generated by combining bits from aa, ab, ba bb and c inputs. see tn1182, latticeecp3 sysdsp usage guide, for further information. next dsp slice previous dsp slice ir ir ir ir ir or or fr = = pr ir
2-24 architecture lattice semiconductor latticee cp3 family data sheet for further information, please refer to tn1182, latticeecp3 sysdsp usage guide . mult dsp element this multiplier element implements a multiply with no addition or accumulator nodes. the two operands, aa and ab, are multiplied and the result is available at the output. the user can enable the input/output and pipeline regis- ters. figure 2-26 shows the mult sysdsp element. figure 2-26. mult sysdsp element r= a b c r = logic (b, c) aa ab ba bb multa multb bmux amux cmux alu a_alu b_alu ir pr pr or rounding a_alu opcode c cin cout srob sroa srib sria c_alu 0 00 from fpga core to fpga core ir = input register pr = pipeline register or = output register fr = flag register next dsp slice previous dsp slice ir ir ir ir ir or or fr = = pr ir
2-25 architecture lattice semiconductor latticee cp3 family data sheet mac dsp element in this case, the two operands, aa and ab, are multiplied and the result is added with the previous accumulated value. this accumulated value is available at the output. the user can enable the input and pipeline registers, but the output register is always enabled. the output register is used to store the accumulated value. the alu is con- figured as the accumulator in the sysdsp slice in the la tticeecp3 family can be initialized dynamically. a regis- tered overflow signal is also available. the overflow conditions are provided later in this document. figure 2-27 shows the mac sysdsp element. figure 2-27. mac dsp element r= a b c r = logic (b, c) aa ab ba bb multa multb bmux amux cmux alu a_alu b_alu i pr pr rounding a_alu opcode c cin cout srob sroa srib sria c_alu 0 00 from fpga core to fpga core ir = input register pr = pipeline register or = output register fr = flag register next dsp slice previous dsp slice ir ir ir ir ir ir or or or fr = = pr
2-26 architecture lattice semiconductor latticee cp3 family data sheet mmac dsp element the latticeecp3 supports a mac with two mu ltipliers. this is called multiply multiply accumu late or mmac. in this case, the two operands, aa and ab, are multiplied and the result is added with the previous accumulated value and with the result of the multiplier operation of operands ba and bb. this accumulated value is available at the output. the user can enable the input and pipeline registers, but the output register is always enabled. the output register is used to store the accumulated value. the alu is configured as the accumulator in the sysdsp slice. a registered overflow signal is also available. the overflow conditions are provided later in this document. figure 2-28 shows the mmac sysdsp element. figure 2-28. mmac sysdsp element r= a b c r = logic (b, c) aa ab ba bb multa multb bmux amux cmux alu a_alu b_alu ir pr or rounding a_alu opcode c cin cout srob sroa srib sria c_alu 0 00 from fpga core to fpga core ir = input register pr = pipeline register or = output register fr = flag register next dsp slice previous dsp slice ir ir ir ir ir or or fr = = pr ir pr
2-27 architecture lattice semiconductor latticee cp3 family data sheet multaddsub dsp element in this case, the operands aa and ab are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands ba and bb. the user can enable the input, output and pipeline registers. figure 2-29 shows the multaddsub sysdsp element. figure 2-29. multaddsub r= a b c r = logic (b, c) aa ab ba bb multa multb bmux amux cmux alu a_alu b_alu ir pr pr rounding a_alu opcode c cin cout srob sroa srib sria c_alu 0 00 from fpga core to fpga core ir = input register pr = pipeline register or = output register fr = flag register next dsp slice previous dsp slice ir ir ir ir ir ir or = = pr or fr or
2-28 architecture lattice semiconductor latticee cp3 family data sheet multaddsubsum dsp element in this case, the operands aa and ab are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands ba and bb of slice 0. additionally, the operands aa and ab are multiplied and the result is added/subtracted with the result of the multiplier operation of operands ba and bb of slice 1. the results of both addition/subtractions are added by the second alu following the slice cascade path. the user can enable the input, output and pipeline registers. figure 2-30 and figure 2-31 show the multaddsubsum sysdsp ele- ment. figure 2-30. multaddsubsum slice 0 r= a b c r = logic (b, c) aa ab ba bb multa multb bmux amux cmux alu a_alu b_alu i pr pr rounding a_alu opcode c cin cout srob sroa srib sria c_alu 0 0 0 from fpga core to fpga core ir = input register pr = pipeline register or = output register fr = flag register next dsp slice previous dsp slice ir ir ir ir ir ir or or or = fr = pr
2-29 architecture lattice semiconductor latticee cp3 family data sheet figure 2-31. multaddsubsum slice 1 advanced sysdsp slice features cascading the latticeecp3 sysdsp slice ha s been enhanced to allow cascading. adder trees are implemented fully in sys- dsp slices, improving the performance. cascading of slic es uses the signals cin, cout and c mux of the slice. addition the latticeecp3 sysdsp slice allows for the bypassing of multipliers and cascading of adder logic. high perfor- mance adder functions are implemented without the use of luts. the maximum width adders that can be imple- mented are 54-bit. rounding the rounding operation is implemented in the alu and is done by adding a constant followed by a truncation oper- ation. the rounding methods supported are: ? rounding to zero (rtz) ? rounding to infinity (rti) ? dynamic rounding ? random rounding ? convergent rounding r= a b c r = logic (b, c) aa ab ba bb multa multb bmux amux cmux alu a_alu b_alu ir pr pr or rounding a_alu opcode c cin cout srob sroa srib sria c_alu 0 00 from fpga core to fpga core ir = input register pr = pipeline register or = output register fr = flag register next dsp slice previous dsp slice ir ir ir ir ir ir or or = fr = pr
2-30 architecture lattice semiconductor latticee cp3 family data sheet alu flags the sysdsp slice provides a number of flags from the alu including: ? equal to zero (eqz) ? equal to zero with mask (eqzm) ? equal to one with mask (eqom) ? equal to pattern with mask (eqpat) ? equal to bit inverted pattern with mask (eqpatb) ? accumulator overflow (over) ? accumulator underflow (under) ? either over or under flow supporting latticeecp2 legacy designs (overunder) clock, clock enable and reset resources global clock, clock enable and reset si gnals from routing are available to every sysdsp slice. from four clock sources (clk0, clk1, clk2, and clk3) one clock is selected for each input register, pipeline register and output register. similarly clock enable (ce) and reset (rst) are selected at each input register, pipeline register and out- put register. resources available in the latticeecp3 family table 2-9 shows the maximum number of multipliers for each member of the latticeecp3 family. table 2-10 shows the maximum available ebr ram blocks in each latticee cp3 device. ebr blocks, together with distributed ram can be used to store variables locally for fast dsp operations. table 2-9. maximum number of dsp slices in the latticeecp3 family table 2-10. embedded sram in the latticeecp3 family device dsp slices 9x9 multiplier 18 x18 multiplier 36x36 multiplier ecp3-17 12 48 24 6 ecp3-35 32 128 64 16 ecp3-70 64 256 128 32 ecp3-95 64 256 128 32 ecp3-150 160 640 320 80 device ebr sram block total ebr sram (kbits) ecp3-17 38 700 ecp3-35 72 1327 ecp3-70 240 4420 ecp3-95 240 4420 ecp3-150 372 6850
2-31 architecture lattice semiconductor latticee cp3 family data sheet programmable i/o cells (pic) each pic contains two pios connected to their respective sysi/o buffers as shown in figure 2-32. the pio block supplies the output data (do) and the tri-state control signal (to) to the sysi/o buffer and receives input from the buffer. table 2-11 provides the pio signal list. figure 2-32. pic diagram onegb ts ina ipa del[3:0] eclk1, eclk2 sclk ce lsr eclk1 eclk2 sclk read dcntl[5:0] dyndel[7:0] dqsi prmdet gsrn ddrlat* ddrclkpol* eclkdqsr* dqclk0* dqclk1* dqsw* clk ceot cei sysio buffer pada ? padb ? lsr gsr * signals are available on left/right/top edges only. ** signals are available on the left and right sides only *** selected pio. iold0 di tristate register block output register block (isi) input register block control muxes read control write control piob pioa oposa oposb onega** onegb** ipb inck indd inb iolt0 i/os in a dqs-12 group, except dqsn (complement of dqs) i/os dqs control block (one per dqs group of 12 i/os)***
2-32 architecture lattice semiconductor latticee cp3 family data sheet two adjacent pios can be joined to provide a differential i/o pair (labeled as ?t? and ?c?) as shown in figure 2-32. the pad labels ?t? and ?c? distinguish the two pios. approximately 50% of the pio pairs on the left and right edges of the device can be configured as true lvds outputs. all i/o pairs can operate as lvds inputs. table 2-11. pio signal list pio the pio contains four blocks: an input register block, output register block, tristate register block and a control logic block. these blocks contain registers for operating in a variety of modes along with the necessary clock and selec- tion logic. input register block the input register blocks for the pios, in the left, right and top edges, contain delay elements and registers that can be used to condition high-speed interface signals, such as ddr memory interfaces and source synchronous inter- faces, before they are passed to the device core. figure 2-33 shows the input register block for the left, right and top edges. the input register block for the bottom edge contains one element to register the input signal and no ddr registers. the following description applies to the input register block for pios in the left, right and top edges only. name type description indd input data register bypassed input. this is not the same port as inck. ipa, ina, ipb, inb input data ports to core for input data oposa, onega 1 , oposb, onegb 1 output data output signals from core. an exception is the onegb port, used for tristate logic at the dqs pad. ce pio control clock enables for input and output block flip-flops. sclk pio control system clock (pclk) for input and output/ts blocks. connected from clock isb. lsr pio control local set/reset eclk1, eclk2 pio control edge clock sources. entire pio selects one of two sources using mux. eclkdqsr 1 read control from dqs_strobe, shifted strobe for memory interfaces only. ddrclkpol 1 read control ensures transfer from dqs domain to sclk domain. ddrlat 1 read control used to guarantee inddrx2 gearing by selectively enabling a d-flip-flop in dat- apath. del[3:0] read control dynamic input delay control bits. inck to clock distribution and pll pio treated as clock pio, path to distribute to primary clocks and pll. ts tristate data tristate signal from core (sdr) dqclk0 1 , dqclk1 1 write control two clocks edges, 90 degrees out of phase, used in output gearing. dqsw 2 write control used for output and tristate logic at dqs only. dyndel[7:0] write control shifting of write clocks fo r specific dqs group, using 6:0 each step is approxi- mately 25ps, 128 steps. bit 7 is an invert (timing depends on input frequency). there is also a static control for this 8-bit setting, enabled with a memory cell. dcntl[6:0] pio control origina l delay code from ddr dll datavalid 1 output data status flag from datavalid logic, us ed to indicate when input data is captured in iologic and valid to core. read for dqs_strobe read signal for ddr memory interface dqsi for dqs_strobe unshift ed dqs strobe from input pad prmbdet for dqs_strobe dqsi biased to go high when dqsi is tristate, goes to input logic block as well as core logic. gsrn control from routing global set/reset 1. signals available on left/right/top edges only. 2. selected pio.
2-33 architecture lattice semiconductor latticee cp3 family data sheet input signals are fed from the sysi/o buffer to the input regi ster block (as signal di). if desired, the in put signal can bypass the register and delay elements and be used directly as a combinatorial signal (indd), a clock (inck) and, in selected blocks, the input to the dqs delay block. if an input delay is desired, designers can select either a fixed delay or a dynamic delay del[3:0]. the delay, if selected, reduces input register hold time requirements when using a global clock. the input block allows three modes of operation. in single data rate (sdr ) the data is registered with the system clock by one of the registers in the single data rate sync register block. in ddr mode, two registers are used to sample the data on the positive and negative edges of the modified dqs (eclkdqsr) in the ddr memory mode or eclk signal when using ddr generic mode, creating two data streams. before entering the core, these two data streams are synchronized to the system clock to generate two data streams. a gearbox function can be implemented in each of the input registers on the left and right sides. the gearbox func- tion takes a double data rate signal applied to pioa and converts it as four data streams, ina, ipa, inb and ipb. the two data streams from th e first set of ddr registers are synchronized to the edge clock and then to the system clock before entering the core. figure 2-30 provides further information on the use of the gearbox function. the signal ddrclkpol controls the pola rity of the clock used in the synchr onization registers. it ensures ade- quate timing when data is transferred to the system clock domain from the eclkdqsr (ddr memory interface mode) or eclk (ddr generic mode). th e ddrlat signal is used to ensure the data transfer fr om the synchroni- zation registers to the clock transfer and gearbox registers. the eclkdqsr, ddrclkpol and ddrlat signals are gener ated in the dqs read co ntrol logic block. see figure 2-37 for an overview of the dqs read control logic. further discussion about using the dqs strobe in this module is discussed in the ddr memory section of this data sheet. please see tn1180, latticeecp3 high-speed i/o interface for more information on this topic.
2-34 architecture lattice semiconductor latticee cp3 family data sheet figure 2-33. ecp3-70/95 (e or ea) input re gister block for left, right and top edges output register block the output register block registers signals from the core of the device before they are passed to the sysi/o buffers. the blocks on the left and right pios contain registers for sdr and full ddr operation. the topside pio block is the same as the left and right sides except it does not support oddrx2 gearing of output logic. oddrx2 gearing is used in ddr3 memory interfaces.the pio blocks on the bottom contain the sdr registers and generic ddr inter- face without gearing. figure 2-34 shows the output register block for pios on the left and right edges. in sdr mode, oposa feeds one of the flip-flops that then feeds the output. the flip-flop can be configured as a dtype or latch. in ddr mode, two of the inputs are fed into registers on the positive edge of the clock. at the next clock cycle, one of the registered outputs is also latched. a multiplexer running off the same clock is used to switch the mux between the 11 and 01 inputs that will then feed the output. a gearbox function can be implemented in the output register block that takes four data streams: oposa, onega, oposb and onegb. all four data inputs are registered on the positive edge of the system clock and two of them are also latched. the data is then output at a high rate using a multiplexer that runs off the dqclk0 and dqclk1 clocks. dqclk0 and dqclk1 are used in this case to transfer data from the system clock to the edge clock domain. these signals are generated in the dqs write control logic block. see figure 2-37 for an overview of the dqs write control logic. please see tn1180, latticeecp3 high-speed i/o interface for more information on this topic. further discussion on using the dqs strobe in this module is discussed in the ddr me mory section of this data sheet. di (from sysio buffer) d q d q d q d q ddrclkpol dynamic delay fixed delay d q l sclk d q d q d q l d q l ina inb ipb ipa d q d q l d q l d q l d q d q ddrlat x0 01 11 config bit inclk** del[3:0] indd d q ce r ddr registers a b df e h g c l k j i clkp x0 01 11 eclk2 synch registers eclkdqsr eclk1 eclk2 clock transfer & gearing registers* * only on the left and right sides. ** selected pio. note: simplified diagram does not show ce/set/rest details. to dqsi** 1 0 1 0 0 1
2-35 architecture lattice semiconductor latticee cp3 family data sheet figure 2-34. ecp3-70/95 (e or ea) output and tristate block for left and right edges tristate register block the tristate register block registers tri-state control signals from the core of the device before they are passed to the sysi/o buffers. the block contains a register for sdr operation and an additional register for ddr operation. in sdr and non-gearing ddr modes, ts input feeds one of the flip-flops that then feeds the output. in ddrx2 mode, the register ts input is fed into another register that is clocked using the dqclk0 and dqclk1 signals. the output of this register is used as a tristate control. isi calibration the setting for inter-symbol interference (isi) cancellation occurs in the output register block. isi correction is only available in the ddrx2 modes. isi calibration settings exist once per output register block, so each i/o in a dqs- 12 group may have a different isi calibration setting. the isi block extends output signals at certain times, as a function of recent signal history. so, if the output pattern consists of a long strings of 0's to long strings of 1's, there are no delays on output signals. however, if there are quick, successive transitions from 010, the block will stretch out the binary 1. th is is because the long trail of 0's will cause these symbols to interfere with the logic 1. likewise, if there are quick, successive transitions from 101, the block will stretch out the binary 0. this bl ock is controlled by a 3-bit delay contro l that can be set in the dqs control logic block. for more information about this topic, please see the list of technical documentation at the end of this data sheet. d q d q ce r d q do d q d q onegb oposa oposb onega d q l l 11 10 00 01 sclk dqclk1 config bit dqclk0 isi d q ce r ts d q a b c d c1 d1 tristate logic output logic to clock transfer registers ddr gearing & isi correction
2-36 architecture lattice semiconductor latticee cp3 family data sheet control logic block the control logic block allows the selection and modification of control signals for use in the pio block. ddr memory support certain pics have additional circuitry to allow the im plementation of high-speed source synchronous and ddr1, ddr2 and ddr3 memory interfaces. the support varies by the edge of the device as detailed below. left and right edges the left and right sides of the pic have fully functional elements supporting ddr1, ddr2, and ddr3 memory interfaces. one of every 12 pios supports the dedicated dqs pins with the dqs control logic block. figure 2-35 shows the dqs bus spanning 11 i/o pins. two of every 12 pios support the dedicated dqs and dqs# pins with the dqs control logic block. bottom edge pics on the bottom edge of the device do not support ddr memory and g eneric ddr interfaces. top edge pics on the top side are similar to the pio elements on the left and right sides but do not support gearing on the output registers. hence, the mode s to support output/tristate ddr3 me mory are removed on the top side. the exact dqs pins are shown in a dual function in the lo gic signal connections table in this data sheet. addi- tional detail is provided in the signal descriptions table. the dqs signal from the bus is used to strobe the ddr data from the memory into input register blocks. interfaces on the left, right and top edges are designed for ddr memories that support 10 bits of data. figure 2-35. dqs grouping on the left, right and top edges dll calibrated dqs delay block source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. for most interfaces , a pll is used for this adjustment . however, in ddr memories the clock pio b pio a pio b pio a assigned dqs pin dqs delay sysio buffer pada "t" padb "c" lvds pair pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair
2-37 architecture lattice semiconductor latticee cp3 family data sheet (referred to as dqs) is not free-running so this approach cannot be used. the dqs delay block provides the required clock alignment for ddr memory interfaces. the delay required for the dqs signal is generated by two dedicated dlls (ddr dll) on opposite side of the device. each dll creates dqs delays in its half of the device as shown in figure 2-36. the ddr dll on the left side will generate delays for all the dqs strobe pins on banks 0, 7 and 6 and ddr dll on the right will generate delays for all the dqs pins on banks 1, 2 and 3. the ddr dll loop compensates for temperature, voltage and pro- cess variations by using the system clock and dll feedback loop. ddr dll communicates the required delay to the dqs delay block using a 7-bit calibration bus (dcntl[6:0]) the dqs signal (selected pios only, as shown in figure 2-35) feeds from the pad through a dqs control logic block to a dedicated dqs routing resource. the dqs control logic block consists of dqs read control logic block that generates control signals for the read side and dqs write control logic that generates the control signals required for the write side. a more detailed dqs control diagram is shown in figure 2-37, which shows how the dqs control blocks interact with the data paths. the dqs read control logic receives the delay generated by the ddr dll on its side and delays the incoming dqs signal by 90 degrees. this delayed eclkdqsr is routed to 10 or 11 dq pads covered by that dqs signal. this block also contains a polarity control logic that ge nerates a ddrclkpol signal, which controls the polarity of the clock to the sync registers in the input register blocks. the dqs read control logic also generates a ddrlat signal that is in the input register block to transfer data from the firs t set of ddr register to the second set of ddr registers when using the ddrx2 gearbox mode for ddr3 memory interface. the dqs write control logic block generates the dqclk0 and dqclk1 clocks used to control the output gearing in the output register block which generates the ddr data output and the dqs output. they are also used to con- trol the generation of the dqs output through the dqs output register block. in addition to the dcntl [6:0] input from the ddr dll, the dqs write control block also uses a dynamic delay dyn del [7:0] attribute which is used to further delay the dqs to accomplish the write leveling found in ddr3 memory . write leveling is controlled by the ddr memory controller implementation. the dyn delay can set 128 possible delay step settings. in addition, the most significant bit will invert the clock for a 180-degree shift of the incoming clock. this will generate the dqsw signal used to generate the dqs output in the dqs output register block. figure 2-36 and figure 2-37 show how the dqs transition signals that are routed to the pios. please see tn1180, latticeecp3 high-speed i/o interface for more information on this topic.
2-38 architecture lattice semiconductor latticee cp3 family data sheet figure 2-36. edge clock, dll calibr ation and dqs local bus distribution dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs bank 0 bank 1 configuration bank bank 2 bank 7 bank 6 bank 3 dqs strobe and transition detect logic i/o ring *includes shared configuration i/os and dedicated configuration i/os. serdes ddr dll (left) ddr dll (right) dqs delay control bus eclk1 eclk2 dqclk0 dqclk1 ddrlat ddrclkpol eclkdqsr datavalid
2-39 architecture lattice semiconductor latticee cp3 family data sheet figure 2-37. dqs local bus polarity control logic in a typical ddr memory interface design, the phase relationship between the incoming delayed dqs strobe and the internal system clock (during the read cycle) is unkn own. the latticeecp3 family contains dedicated circuits to transfer data between these domains. a clock polarity se lector is used to prevent set-up and hold violations at the domain transfer between dqs (delayed) and the system cl ock. this changes the edge on which the data is reg- istered in the synchronizing registers in the input register block. this requires evaluation at the start of each read cycle for the correct clock polarity. prior to the read operation in ddr me mories, dqs is in tristate (pulled by termination). the ddr memory device drives dqs low at the start of the preamble state. a dedicated circuit detects the first dqs rising edge after the pre- amble state. this signal is used to control the polarity of the clock to the synchronizing registers. ddr3 memory support latticeecp3 supports the read and write leveling required for ddr3 memory interfaces. read leveling is supported by the use of the ddrclkpol and the ddrlat signals generated in the dqs read control logic block. these signals dynamically control the capture of the data with respect to the dqs at the input register block. ddr dll dqs write control logic dqs read control logic data output register block dqclk0 dqclk1 dqsw ddrlat ddrclkpol eclkdqsr dcntl[6:0] data input register block dqs pad ddr data pad dqs output register block dqs delay block
2-40 architecture lattice semiconductor latticee cp3 family data sheet to accomplish write leveling in ddr3, ea ch dqs group has a slightly different delay that is set by dyn delay[7:0] in the dqs write control logic block. the dyn delay can set 128 possible delay step settings. in addition, the most significant bit will invert the clock for a 180-degree shift of the incoming clock. latticeecp3 input and output registers can also support ddr gearing that is used to receive and transmit the high speed ddr data from and to the ddr3 memory. latticeecp3 supports the 1.5v sstl i/o standard required for the ddr3 memory interface. in addition, it supports on-chip termination to vtt on the ddr3 memory input pins. for more information, refer to the sysio section of this data sheet. please see tn1180, latticeecp3 high-speed i/o interface for more information on ddr memory interface imple- mentation in latticeecp3. sysi/o buffer each i/o is associated with a flexible buffer referred to as a sysi/o buffer. these buffers are arranged around the periphery of the device in groups referred to as banks. the sysi/o buffers allow users to implement the wide variety of standards that are found in today?s systems including lvds, blvds, hstl, sstl class i & ii, lvcmos, lvttl, lvpecl, pci. sysi/o buffer banks latticeecp3 devices have six sysi/o buffer banks: six bank s for user i/os arranged two per side. the banks on the bottom side are wraparounds of the banks on the lower right and left sides. the seventh sysi/o buffer bank (config- uration bank) is located adjacent to bank 2 and has dedicated/shared i/os for configuration. when a shared pin is not used for configuration it is available as a user i/o. each bank is capable of supporting multiple i/o standards. each sysi/o bank has its own i/o supply voltage (v ccio ). in addition, each bank, except the configuration bank, has voltage references, v ref1 and v ref2 , which allow it to be completely independent from the others. the config- uration bank top side shares v ref1 and v ref2 from sysi/o bank 1 and right side shares v ref1 and v ref2 from sysi/o bank 2. figure 2-38 shows the seven banks and their associated supplies. in latticeecp3 devices, single-ended output buffers and ratioed input buffers (lvttl, lvcmos and pci) are pow- ered using v ccio . lvttl, lvcmos33, lvcmos25 and lvcmos12 can also be set as fixed threshold inputs inde- pendent of v ccio . each bank can support up to two separate v ref voltages, v ref1 and v ref2 , that set the threshold for the refer- enced input buffers. some dedicated i/o pins in a bank c an be configured to be a reference voltage supply pin. each i/o is individually configurable based on the bank?s supply and reference voltages.
2-41 architecture lattice semiconductor latticee cp3 family data sheet figure 2-38. latticeecp3 banks latticeecp3 devices contain two types of sysi/o buffer pairs. 1. top (bank 0 and bank 1) and bottom sysi/o buffer pairs (single-ended outputs only) ? the sysi/o buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). one of the referenced input buffers can also be con - figured as a differential input. only the top edge buffers have a programmable pci clamp. ? ? the two pads in the pair are described as ?true? and ?c omp?, where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. ? ? on the top and bottom sides, there is no support for programmable on-chip input termination, which is required for dq and dqs pins for ddr3 interface. this side is ideal for addr/cmd signals of ddr3, general purpose ? i/o, pci, tr-lvds (transition reduc ed lvds) or lvds inputs. only the top i/o banks support hot socketing with i dk specified under the hot socketing specifications. the configuration bank is not hot-socketable. v ref1(0) gnd v ccio0 v ref2(0) v ref1(1) gnd v ccio1 v ref2(1) v ref1(7) gnd v ccio7 v ref2(7) v ref1(2) gnd v ccio2 v ref2(2) v ref1(3) gnd v ccio3 v ref2(3) right bank 2 configuration bank bank 3 bank 7 bank 6 v ref1(6) gnd v ccio6 v ref2(6) bank 0 bank 1 bottom jtag bank serdes quads left top
2-42 architecture lattice semiconductor latticee cp3 family data sheet 2. left and right (banks 2, 3, 6 and 7) sysi/o buffer pairs (50% differential and 100% single-ended out- puts) ? the sysi/o buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. one of the referenced input buffers can also be configured as a differential input. in these banks the two pads in the pair are described as ?true? and ?comp?, where the true pad is associated with the positive side of the differential i/o, and the comp (complementary) pad is associated with the negative side of the differential i/o. ? ? in addition, programmable on-chip input termination (parallel or differential, static or dynamic) is supported on these sides, which is required for ddr3 interface. however, there is no support for hot-socketing on these sides as the clamp is always present. ? ? lvds, rsds, pplvds and mini-lvds differential output drivers are available on 50% of the buffer pairs on the left and right banks. 3. configuration bank sysi/o buffer pairs (single-ende d outputs, only on shared pins when not used by configuration) ? the sysi/o buffers in the configuration bank consist of single-ended output drivers and single-ended input buf- fers (both ratioed and referenced). the referenced input buffer can also be configured as a differential input. ? ? the two pads in the pair are described as ?true? and ?c omp?, where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. programmable pci clamps are only available on top banks (p ci clamps are used primarily on inputs and bidirec- tional pads to reduce ringing on the receiving end) can also be used on inputs. typical sysi/o i/o be havior during power-up the internal power-on-reset (por ) signal is deactivated when v cc , v ccio8 and v ccaux have reached satisfactory levels. after the por signal is deactiva ted, the fpga core logic becomes active . it is the user?s responsibility to ensure that all other v ccio banks are active with valid input logic levels to properly control the output logic states of all the i/o banks that are critical to the application. for more information about cont rolling the output logic state with valid input logic levels during power-up in latticeecp3 devices, see the list of technical documentation at the end of this data sheet. the v cc and v ccaux supply the power to the fpga core fabric, whereas the v ccio supplies power to the i/o buf- fers. in order to simplify system design while providing consistent and predictable i/o behavior, it is recommended that the i/o buffers be powered-up prior to the fpga core fabric. v ccio supplies should be powered-up before or together with the v cc and v ccaux supplies. supported sysi/o standards the latticeecp3 sysi/o buffer supports both single-ended and differential standards. single-ended standards can be further subdivided into lvcmos, lvttl and other standards. the buffers support the lvttl, lvcmos 1.2v, 1.5v, 1.8v, 2.5v and 3.3v standards. in the lvcmos and lvttl modes, the buffer has individual configuration options for drive strength, slew rates, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. other single-ended standards supported include sstl and hstl. differential standards supported include lvds, blvds, lvpecl, mlvds, rsds, mini-lvds, pplvds (point-to-point lvds), trlvds (transition reduced lvds), differential sstl and differential hstl. tables 2-13 and 2-14 show the i/o standards (together with their supply and reference voltages ) supported by latticeecp3 devices. fo r further information on utilizing the sysi/o buffer to support a variety of standards please see tn1177, latticeecp3 sysio usage guide .
2-43 architecture lattice semiconductor latticee cp3 family data sheet on-chip programmable termination the latticeecp3 supports a variety of programm able on-chip terminations options, including: ? dynamically switchable single ende d termination for sstl15 inputs with programmable resistor values of 40, 50, or 60 ohms. this is particularly useful for low power jedec compliant ddr 3 memory controller imple- mentations. external termination to vtt should be used for ddr2 me mory controller implementation. ? common mode termination of 80, 100, 120 ohms for differential inputs figure 2-39. on-chip termination see table 2-12 for termination options for input modes. table 2-12. on-chip termination options for input modes io_type terminate to vtt 1, 2 diffrential termination resistor 1 lvds25 t 80, 100, 120 blvds25 t 80, 100, 120 mlvds t 80, 100, 120 hstl18_i 40, 50, 60 t hstl18_ii 40, 50, 60 t hstl18d_i 40, 50, 60 t hstl18d_ii 40, 50, 60 t hstl15_i 40, 50, 60 t hstl15d_i 40, 50, 60 t sstl25_i 40, 50, 60 t sstl25_ii 40, 50, 60 t sstl25d_i 40, 50, 60 t sstl25d_ii 40, 50, 60 t sstl18_i 40, 50, 60 t sstl18_ii 40, 50, 60 t sstl18d_i 40, 50, 60 t sstl18d_ii 40, 50, 60 t sstl15 40, 50, 60 t sstl15d 40, 50, 60 t 1. terminate to vtt and diffrential termination resistor when turn on can only have one setting per bank. only left and ri ght banks have this feature. use of terminate to vtt and diffrential termination resistor are mutually exclusive in an i/o bank. on-chip termination tolerance +/- 20% 2. external termination to vtt should be used when implementing ddr2 memory controller. parallel single-ended input differential input zo + - vtt control signal off-chip on-chip programmable resistance (40, 50 and 60 ohms) z0 z0 + - off-chip on-chip vtt* *vtt must be left floating for this termination
2-44 architecture lattice semiconductor latticee cp3 family data sheet please see tn1177, latticeecp3 sysio usage guide for on-chip termination usage and value ranges. equalization filter equalization filtering is available for single-ended inputs on both true and complementary i/os, and for differential inputs on the true i/os on the left, right, and top sides. equalization is required to compensate for the difficulty of sampling alternating logic transitions with a relatively slow slew rate. it is considered the most useful for the input ddrx2 modes, used in ddr3 memory, lvds, or trlvds signaling. equalization f ilter acts as a tunable filter with settings to determine the level of correction. in the latticeecp3 devices, there are four settings available: 0 (none), 1, 2 and 3. the default setting is 0. the equalization logic resides in the sysi/o buffers, the two bits of setting is set uniquely in each input iologic block. therefore, each sysi/o can have a unique equalization setting within a dqs-12 group. hot socketing latticeecp3 devices have been carefully designed to ensure predictable behavior during power-up and power- down. during power-up and power-down sequences, the i/os remain in tri-state until the power supply voltage is high enough to ensure reliable operation. in addition, leak age into i/o pins is controlled within specified limits. please refer to the hot socketing specifications in th e dc and switching characteristics in this data sheet. serdes and pcs (physi cal coding sublayer) latticeecp3 devices feature up to 16 channels of embedded serdes/pcs arranged in quads at the bottom of the devices supporting up to 3.2gbps data rate. figure 2-40 shows the position of the quad blocks for the latticeecp3- 150 devices. table 2-14 shows the location of available serdes quads for all devices. the latticeecp3 serdes/pcs supports a range of popular serial protocols, including: ? pci express 1.1 ? ethernet (xaui, gbe - 1000 base cs/sx/lx and sgmii) ? serial rapidio ? smpte sdi (3g, hd, sd) ?cpri ? sonet/sdh (sts-3, sts-12, sts-48) each quad contains four dedicated serdes for high speed, fu ll duplex serial data transfer. each quad also has a pcs block that interfaces to the serdes channels and contai ns protocol specific digital logic to support the stan- dards listed above. the pcs block also contains interface logic to the fpga fabric. all pcs logic for dedicated pro- tocol support can also be bypassed to allow raw 8-bit or 10-bit interfaces to the fpga fabric. even though the serdes/pcs blocks are arranged in quads, multiple baud rates can be supported within a quad with the use of dedicated, per channel ? 1, ? 2 and ? 11 rate dividers. additionally, multiple quads can be arranged together to form larger data pipes. for information on how to use the serdes/pcs blocks to support specific protocols, as well on how to combine multiple protocols and baud rates within a device, please refer to tn1176, latticeecp3 serdes/pcs usage guide .
2-45 architecture lattice semiconductor latticee cp3 family data sheet figure 2-40. serdes/pcs quads (latticeecp3-150) table 2-13. latticeecp3 serdes standard support standard data rate (mbps) number of general/link width encoding style pci express 1.1 2500 x1, x2, x4 8b10b gigabit ethernet 1250, 2500 x1 8b10b sgmii 1250 x1 8b10b xaui 3125 x4 8b10b serial rapidio type i, serial rapidio type ii, serial rapidio type iii 1250, 2500, 3125 x1, x4 8b10b cpri-1, cpri-2, cpri-3, cpri-4 614.4, 1228.8, 2457.6, 3072.0 x1 8b10b sd-sdi (259m, 344m) 143 1 , 177 1 , 270, 360, 540 x1 nrzi/scrambled hd-sdi (292m) 1483.5, 1485 x1 nrzi/scrambled 3g-sdi (424m) 2967, 2970 x1 nrzi/scrambled sonet-sts-3 2 155.52 x1 n/a sonet-sts-12 2 622.08 x1 n/a sonet-sts-48 2 2488 x1 n/a 1. for slower rates, the serdes are bypassed and cml si gnals are directly connected to the fpga routing. 2. the sonet protocol is supported in 8-bit serdes mode. see tn1176 lattice ecp3 serdes/pcs usage guide for more information. sysio bank 0 sysio bank 1 ch0 ch3 ch2 ch1 serdes/pcs quad d ch0 ch3 ch2 ch1 ch0 ch3 ch2 ch1 ch0 ch3 ch2 ch1 sysio bank 7 sysio bank 2 serdes/pcs quad b serdes/pcs quad a serdes/pcs quad c sysio bank 6 sysio bank 3 configuration bank
2-46 architecture lattice semiconductor latticee cp3 family data sheet table 2-14. available serdes quads per latticeecp3 devices serdes block a serdes receiver channel may receive the serial differential data stream, equalize the signal, perform clock and data recovery (cdr) and de-serialize the data stream before passing the 8- or 10-bit data to the pcs logic. the serdes transmitter channel may receive the parallel 8- or 10-bit data, serialize the data and transmit the serial bit stream through the differential drivers. figure 2-41 shows a single-channel serdes/pcs block. each serdes channel provides a recovered clock and a serdes transmit clock to the pcs block and to the fpga core logic. each transmit channel, receiver channel, and serdes pll shares the same power supply (vcca). the output and input buffers of each channel have their own independent power supplies (vccob and vccib). figure 2-41. simplified channel block diagram for serdes/pcs block pcs as shown in figure 2-41, the pcs receives the parallel digital data from the deserializer and selects the polarity, performs word alignment, decodes (8b/10b), provides clock tolerance compensation and transfers the clock domain from the recovered clock to the fpga clock via the down sample fifo. for the transmit channel, the pcs block receives the parallel data from the fpga core, encodes it with 8b/10b, selects the polarity and passes the 8/10 bit data to the transmit serdes channel. the pcs also provides bypass modes that allow a direct 8-bit or 10-bit interface from the serdes to the fpga logic. the pcs interface to the fpga can also be programmed to run at 1/2 speed for a 16-bit or 20-bit interface to the fpga logic. sci (serdes client interface) bus the serdes client interface (sci) is an ip interface that allows the serdes/pcs quad block to be controlled by registers rather than the configuration memory cells. it is a simple register configuration interface that allows serdes/pcs configuration without power cycling the device. package ecp3-17 ecp3-35 ecp3-70 ecp3-95 ecp3-150 256 ftbga 1 1 ? ? ? 484 ftbga 1111 672 ftbga?1222 1156 ftbga ? ? 3 3 4 hdoutp hdoutn * 1/8 or 1/10 line rate deserializer 1:8/1:10 word alignment 8b10b decoder serializer 8:1/10:1 8b10b encoder serdes pcs bypass bypass bypass bypass transmitter receiver recovered clock* serdes transmit clock* receive clock transmit clock serdes transmit clock receive data transmit data clock/data recovery clock data rx_refclk hdinp hdinn equalizer bypass downsample fifo upsample fifo recovered clock tx pll tx refclk polarity adjust polarity adjust ctc fpga core
2-47 architecture lattice semiconductor latticee cp3 family data sheet the isplever design tools from lattice support all modes of the pcs. mo st modes are dedicate d to applications associated with a specific industry standard data prot ocol. other more general purpose modes allow users to define their own operation. with isplever, the user can define the mode for each quad in a design. popular standards such as 10gb ethernet, x4 pci expre ss and 4x serial rapidio can be implemented using ip (available through lattice), a single quad (four serdes cha nnels and pcs) and some additional logic from the core. the latticeecp3 family also supports a wide range of primary and secondary protocols. within the same quad, the latticeecp3 family can support mixed pr otocols with semi-independent clocking as long as the required clock fre- quencies are integer x1, x2, or x11 multiples of each other. table 2-15 lists the allowable combination of primary and secondary protocol combinations. flexible quad serdes architecture the latticeecp3 family serdes architecture is a quad-based architecture. for most serdes settings and stan- dards, the whole quad (consisting of four serdes) is treated as a unit. this helps in silicon area savings, better utilization and overall lower cost. however, for some specific standards, the latticeecp3 quad arch itecture provides flexib ility; more than one stan- dard can be supported within the same quad. table 2-15 shows the standards can be mixed and matched within the same quad. in general, the serdes stan- dards whose nominal data rates are either the same or a defined subset of each other, can be supported within the same quad. in table 2-15, the primary protocol column refers to the standard that determines the reference clock and pll settings. the secondary protocol column shows the other standard that can be supported within the same quad. furthermore, table 2-15 also implies that more than two standards in the same quad can be supported, as long as they conform to the data rate and reference clock requirements. for example, a quad may contain pci express 1.1, sgmii, serial rapidio type i and serial rapidio type ii, all in the same quad. table 2-15. latticeecp3 primary and secondary protocol support for further information on serdes, please see tn1176, latticeecp3 serdes/pcs usage guide . ieee 1149.1-compliant boundary scan testability all latticeecp3 devices have boundary scan cells that are accessed through an ieee 1149.1 compliant test access port (tap). this allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. in ternal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. the test primary protocol secondary protocol pci express 1.1 sgmii pci express 1.1 gigabit ethernet pci express 1.1 serial rapidio type i pci express 1.1 serial rapidio type ii serial rapidio type i sgmii serial rapidio type i gigabit ethernet serial rapidio type ii sgmii serial rapidio type ii gigabit ethernet serial rapidio type ii serial rapidio type i cpri-3 cpri-2 and cpri-1 3g-sdi hd-sdi and sd-sdi
2-48 architecture lattice semiconductor latticee cp3 family data sheet access port consists of dedicated i/os: tdi, tdo, tck and tms. the test access port has its own supply voltage v ccj and can operate with lvcmos3.3, 2.5, 1.8, 1.5 and 1.2 standards. for more information, please see tn1169, latticeecp3 sysconfig usage guide . device configuration all latticeecp3 devices contain two ports that can be us ed for device configuration. the test access port (tap), which supports bit-wide configuration, and the sysconfig port, support dual-byte, byte and serial configuration. the tap supports both the ieee standard 1149.1 boundary scan specification and the ieee standard 1532 in- system configuration specification. the sysconfig port includes seven i/os used as dedicated pins with the remaining pins used as dual-use pins. see tn1169, latticeecp3 sysconfig usage guide for more information about using the dual-use pins as general purpose i/os. there are various ways to configure a latticeecp3 device: 1. jtag 2. standard serial peripheral interface (spi and spim modes) - interface to boot prom memory 3. system microprocessor to drive a x8 cpu port (pcm mode) 4. system microprocessor to drive a serial slave spi port (sspi mode) 5. generic byte wide flash with a machxo? device, providing control and addressing on power-up, the fpga sram is ready to be configured using the selected sysconfig port. once a configuration port is selected, it will rema in active throughout that c onfiguration cycle. the ieee 1149 .1 port can be activated any time after power-up by sending the appropriate command through the tap port. latticeecp3 devices also support the slave spi interface. in this mode, the fpga behaves like a spi flash device (slave mode) with the spi port of the fpga to perform read-write operations. enhanced configuration options latticeecp3 devices have enhanced configuration features such as: decryption sup port, transfr? i/o and dual- boot image support. 1. transfr (transparent field reconfiguration) ? transfr i/o (tfr) is a unique lattice technology that allows users to update their logic in the field without interrupting system operation using a single ispvm command. transfr i/o allows i/o states to be frozen dur - ing device configuration. this allows the device to be field updated with a mini mum of system disruption and downtime. see tn1087, minimizing system interruption during configuration using transfr technology for details. 2. dual-boot image support ? dual-boot images are supported for applications requiring reliable remote updates of configuration data for the system fpga. after the system is running with a basic configuration, a new boot image can be downloaded remotely and stored in a separate location in the configuration storage device. any time after the update the latticeecp3 can be re-booted from this new configuration file. if there is a problem, such as corrupt data dur- ing download or incorrect version number with this new boot image, the latticeecp3 device can revert back to the original backup golden configuration and try again. this all can be done without power cycling the system. for more information, please see tn1169, latticeecp3 sysconfig usage guide . soft error detect (sed) support latticeecp3 devices have dedicated logic to perform cycle redundancy code (crc) checks. during configura- tion, the configuration data bitstream can be checked with the crc logic block. in addition, th e latticeecp3 device
2-49 architecture lattice semiconductor latticee cp3 family data sheet can also be programmed to utilize a so ft error detect (sed) mode that checks for soft errors in configuration sram. the sed operation can be run in the background during user mode. if a soft error occurs, during user mode (normal operation) the device can be programmed to generate an error signal. for further information on sed support, please see tn1184, latticeecp3 soft error detection (sed) usage guide . external resistor latticeecp3 devices require a single external, 10k ohm 1% value between the xres pin and ground. device configuration will not be comple ted if this resistor is miss ing. there is no boundary sca n register on the external resistor pad. on-chip oscillator every latticeecp3 device has an internal cmos oscillator wh ich is used to derive a master clock (mclk) for con- figuration. the oscillato r and the mclk run cont inuously and are available to user logic after configuration is com- pleted. the software default value of the mclk is nominally 2.5mhz. table 2-16 lists all the available mclk frequencies. when a different master clock is selected during the design process, the following sequence takes place: 1. device powers up with a nominal master clock frequency of 3.1mhz. 2. during configuration, users select a different master clock frequency. 3. the master clock frequency changes to the selected frequency once the clock configuration bits are received. 4. if the user does not select a master clock frequency, th en the configuration bitstream defaults to the mclk fre- quency of 2.5mhz. this internal cmos oscillator is availabl e to the user by routing it as an in put clock to the clock tree. for further information on the use of this oscillator for configuration or user mode, please see tn1169, latticeecp3 syscon- fig usage guide . table 2-16. selectable master clock (mclk) frequencies during configuration (nominal) density shifting the latticeecp3 family is designed to ensure that different density devices in the same family and in the same package have the same pinout. furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. in many cases, it is also possible to shift a lower uti- lization design targeted for a high-density device to a lowe r density device. however, the exact details of the final resource utilization will impact the likelih ood of success in each case. an ex ample is that some user i/os may become no connects in smalle r devices in the same packge. mclk (mhz) mclk (mhz) mclk (mhz) 2.5 1 10 41 3.1 13 45 4.3 15 51 5.4 20 55 6.9 26 60 8.1 30 130 9.2 34 ? 1. software default mclk frequency. hardware default is 3.1mhz.
www.latticesemi.com 3-1 ds1021 dc and switching_01.7 march 2010 preliminary data sheet ds1021 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. recommended operating conditions 1 absolute maximum ratings 1, 2, 3 1. stress above those listed under the ?absol ute maximum ratings? may cause permanent dam age to the device. functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. compliance with the lattice thermal management document is required. 3. all voltages referenced to gnd. supply voltage v cc . . . . . . . . . . . . . . . . . . . -0.5 to 1.32v supply voltage v ccaux . . . . . . . . . . . . . . . . -0.5 to 3.75v supply voltage v ccj . . . . . . . . . . . . . . . . . . -0.5 to 3.75v output supply voltage v ccio . . . . . . . . . . . -0.5 to 3.75v input or i/o tristate voltage applied 4 . . . . . . -0.5 to 3.75v storage temperature (ambient) . . . . . . . . . -65 to 150c junction temperature (tj) . . . . . . . . . . . . . . . . . . +125c 4. overshoot and undershoot of -2v to (v ihmax + 2) volts is permitted for a duration of <20ns. symbol parameter min. max. units v cc 2 core supply voltage 1.14 1.26 v v ccaux 2, 4 auxiliary supply voltage, terminating resistor switching power supply (serdes) 3.135 3.465 v v ccpll pll supply voltage 3.135 3.465 v v ccio 2, 3 i/o driver supply voltage 1.14 3.465 v v ccj 2 supply voltage for ieee 1149.1 test access port 1.14 3.465 v v ref1 and v ref2 input reference voltage 0.5 1.7 v v tt 5 termination voltage 0.5 1.3125 v t jcom junction temperature, commercial operation 0 85 c t jind junction temperature, industrial operation -40 100 c serdes external power supply 6 v ccib input buffer power supply (1.2v) 1.14 1.26 v input buffer power supply (1.5v) 1.425 1.575 v v ccob output buffer power supply (1.2v) 1.14 1.26 v output buffer power supply (1.5v) 1.425 1.575 v v cca transmit, receive, pll and reference clock buffer power supply 1.14 1.26 v 1. for correct operation, all supplies except v ref and v tt must be held in their valid operation range. this is true independent of feature usage. 2. if v ccio or v ccj is set to 1.2v, they must be connected to the same power supply as v cc. if v ccio or v ccj is set to 3.3v, they must be con- nected to the same power supply as v ccaux . 3. see recommended voltages by i/o standard in subsequent table. 4. v ccaux ramp rate must not exceed 30mv/s during power-up when transitioning between 0v and 3.3v. 5. if not used, v tt should be left floating. 6. see tn1176, latticeecp3 serdes/pcs usage guide for information on board considerations for serdes power supplies. latticeecp3 family data sheet dc and switching characteristics
3-2 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet hot socketing specifications 1, 3, 4 hot socketing requirements 1, 2 esd performance symbol parameter condition min. typ. max. units idk_hs 2 input or i/o leakage current 0 ?? v in ? v ih (max.) ? ? +/-1 ma idk 5 input or i/o leakage current 0 ? v in < v ccio ??+/-1ma v ccio ? v in ? v ccio + 0.5v ? 18 ? ma 1. v cc , v ccaux and v ccio should rise/fall monotonically. 2. applicable to general purpose i/o pins in top i/o banks only. 3. i dk is additive to i pu , i pw or i bh . 4. lvcmos and lvttl only. 5. applicable to general purpose i/o pins in left and right i/o banks only. description min. typ. max. units input current per serdes i/o pin when device is powered down and inputs driven. ?? 8ma 1. assumes the device is powered down, all supplies grounded, both p and n inputs driven by cml driver with maximum allowed vcco b (1.575v), 8b10b data, internal ac coupling. 2. each p and n input must have less than the specified maximum input current. for a 16-channel device, the total input current would be 8ma*16 channels *2 input pins per channel = 256ma pin group esd stress min. units all pins hbm 1000 v all pins except high-speed serial and xres 1 cdm 500 v high-speed serial inputs cdm 400 v 1. the xres pin on the tw device passes cdm testing at 250v.
3-3 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet dc electrical characteristics over recommended operating conditions symbol parameter condition min. typ. max. units i il , i ih 1, 4 input or i/o low leakage 0 ? v in ? (v ccio - 0.2v) ? ? 10 a i ih 1, 3 input or i/o high leakage (v ccio - 0.2v) < v in ? 3.6v ? ? 150 a i pu i/o active pull-up current 0 ? v in ? 0.7 v ccio -30 ? -210 a i pd i/o active pull-down current v il (max) ? v in ? v ccio 30 ? 210 a i bhls bus hold low sustaining current v in = v il (max) 30 ? ? a i bhhs bus hold high sustaining current v in = 0.7 v ccio -30 ? ? a i bhlo bus hold low overdrive current 0 ? v in ? v ccio ??210a i bhho bus hold high overdrive current 0 ? v in ? v ccio ??-210a v bht bus hold trip points 0 ? v in ? v ih (max) v il (max) ? v ih (min) v c1 i/o capacitance 2 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = 1.2v, v io = 0 to v ih (max) ?8?pf c2 dedicated input capacitance 2 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = 1.2v, v io = 0 to v ih (max) ?6?pf 1. input or i/o leakage current is measured wi th the pin configured as an input or as an i/o with the output driver tri-stated. it is not measured with the output driver active. bus maintenance circuits are disabled. 2. t a 25 o c, f = 1.0mhz. 3. applicable to general purpose i/os in top and bottom banks. 4. when used as v ref , maximum leakage= 25a.
3-4 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet latticeecp3 supply current (standby) 1, 2, 3, 4, 5, 6 over recommended operating conditions symbol parameter device typical units i cc core power supply current ecp-17ea 89.30 ma ecp3-35ea 89.30 ma ecp3-70e 226.30 ma ecp3-70ea 230.60 ma ecp3-95e 226.30 ma ecp3-95ea 230.60 ma ecp3-150ea 370.80 ma i ccaux auxiliary power supply current ecp-17ea 28.20 ma ecp3-35ea 28.20 ma ecp3-70e 30.60 ma ecp3-70ea 30.60 ma ecp3-95e 30.60 ma ecp3-95ea 30.60 ma ecp3-150ea 45.70 ma i ccpll pll power supply current (per pll) ecp-17ea 0.05 ma ecp3-35ea 0.03 ma ecp3-70e 0.02 ma ecp3-70ea 0.02 ma ecp3-95e 0.02 ma ecp3-95ea 0.02 ma ecp3-150ea 0.02 ma i ccio bank power supply current (per bank) ecp-17ea 1.38 ma ecp3-35ea 1.38 ma ecp3-70e 1.43 ma ecp3-70ea 1.43 ma ecp3-95e 1.43 ma ecp3-95ea 1.43 ma ecp3-150ea 1.46 ma i ccj jtag power supply current all devices 2.50 ma i cca transmit, receive, pll and reference clock buffer power supply ecp-17ea 5.90 ma ecp3-35ea 5.90 ma ecp3-70e 17.80 ma ecp3-70ea 17.80 ma ecp3-95e 17.80 ma ecp3-95ea 17.80 ma ecp3-150ea 23.80 ma 1. for further information on supply current, please see the li st of technical documentation at the end of this data sheet. 2. assumes all outputs are trista ted, all inputs are configured as lvcmos and held at the v ccio or gnd. 3. frequency 0 mhz. 4. pattern represents a ?blank? configuration data file. 5. t j = 85c, power supplies at nominal voltage. 6. to determine the latticeecp3 peak start-up current data, use the power calculator tool in isplever.
3-5 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet serdes power supply requirements 1, 2, 3 over recommended operating conditions symbol description typ. max. units standby (power down) i cca-sb v cca current (per channel) 3 5 ma i ccib-sb input buffer current (per channel) ? ? ma i ccob-sb output buffer current (per channel) ? ? ma operating (data rate = 3.2 gbps) i cca-op v cca current (per channel) 68 77 ma i ccib-op input buffer current (per channel) 5 7 ma i ccob-op output buffer current (per channel) 19 25 ma operating (data rate = 2.5 gbps) i cca-op v cca current (per channel) 66 76 ma i ccib-op input buffer current (per channel) 4 5 ma i ccob-op output buffer current (per channel) 15 18 ma operating (data rate = 1.25 gbps) i cca-op v cca current (per channel) 62 72 ma i ccib-op input buffer current (per channel) 4 5 ma i ccob-op output buffer current (per channel) 15 18 ma operating (data rate = 250 mbps) i cca-op v cca current (per channel) 55 65 ma i ccib-op input buffer current (per channel) 4 5 ma i ccob-op output buffer current (per channel) 14 17 ma 1. equalization enabled, pre-emphasis disabled. 2. one quarter of the total quad power (includes contributi on from common circuits, all channels in the quad operating, pre-emphasis disabled, equalization enabled). 3. pre-emphasis adds 20ma to icca-op data.
3-6 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet sysi/o recommended operating conditions standard v ccio v ref (v) min. typ. max. min. typ. max. lv c m o s 3 3 2 3.135 3.3 3.465 ? ? ? lv c m o s 2 5 2 2.375 2.5 2.625 ? ? ? lvcmos18 1.71 1.8 1.89 ? ? ? lvcmos15 1.425 1.5 1.575 ? ? ? lv c m o s 1 2 2 1.14 1.2 1.26 ? ? ? lv t t l 3 3 2 3.135 3.3 3.465 ? ? ? pci33 3.135 3.3 3.465 ? ? ? sstl15 3 1.43 1.5 1.57 0.68 0.75 0.9 sstl18_i, ii 2 1.71 1.8 1.89 0.833 0.9 0.969 sstl25_i, ii 2 2.375 2.5 2.625 1.15 1.25 1.35 sstl33_i, ii 2 3.135 3.3 3.465 1.3 1.5 1.7 hstl15_i 2 1.425 1.5 1.575 0.68 0.75 0.9 hstl18_i, ii 2 1.71 1.8 1.89 0.816 0.9 1.08 lv d s 2 5 2 2.375 2.5 2.625 ? ? ? mlvds25 1 2.375 2.5 2.625 ? ? ? lvpecl33 1, 2 3.135 3.3 3.465 ? ? ? mini lvds ?????? blvds25 1, 2 2.375 2.5 2.625 ? ? ? rsds25 1, 2 2.375 2.5 2.625 ? ? ? rsds25e 1, 2 2.375 2.5 2.625 ? ? ? trlvds 3.14 3.3 3.47 ? ? ? pplvds 3.14/2.25 3.3/2.5 3.47/2.75 ? ? ? sstl15d 1.43 1.5 1.57 ? ? ? sstl18d_i 2 , ii 2 1.71 1.8 1.89 ? ? ? sstl25d_ i 2 , ii 2 2.375 2.5 2.625 ? ? ? sstl33d_ i 2 , ii 2 3.135 3.3 3.465 ? ? ? hstl15d_ i 2 1.425 1.5 1.575 ? ? ? hstl18d_ i 2 , ii 2 1.71 1.8 1.89 ? ? ? 1. inputs on chip. outputs are implemented with the addition of external resistors. 2. for input voltage compatibility, refer to the "mixed voltage support" section of tn1177, latticeecp3 sysio usage guide .
3-7 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet sysi/o single-ended dc el ectrical characteristics input/output standard v il v ih v ol max. (v) v oh min. (v) i ol 1 (ma) i oh 1 (ma) min. (v) max. (v) min. (v) max. (v) lvcmos33 -0.3 0.8 2.0 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos25 -0.3 0.7 1.7 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos18 -0.3 0.35 v ccio 0.65 v ccio 3.6 0.4 v ccio - 0.4 16, 12, 8, 4 -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos15 -0.3 0.35 v ccio 0.65 v ccio 3.6 0.4 v ccio - 0.4 8, 4 -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos12 -0.3 0.35 v cc 0.65 v cc 3.6 0.4 v ccio - 0.4 6, 2 -6, -2 0.2 v ccio - 0.2 0.1 -0.1 lvttl33 -0.3 0.8 2.0 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 pci33 -0.3 0.3 v ccio 0.5 v ccio 3.6 0.1 v ccio 0.9 v ccio 1.5 -0.5 sstl18_i -0.3 v ref - 0.125 v ref + 0.125 3.6 0.4 v ccio - 0.4 6.7 -6.7 sstl18_ii (ddr2 memory) -0.3 v ref - 0.125 v ref + 0.125 3.6 0.28 v ccio - 0.28 8-8 11 -11 sstl2_i -0.3 v ref - 0.18 v ref + 0.18 3.6 0.54 v ccio - 0.62 7.6 -7.6 12 -12 sstl2_ii (ddr2 memory) -0.3 v ref - 0.18 v ref + 0.18 3.6 0.35 v ccio - 0.43 15.2 -15.2 20 -20 sstl3_i -0.3 v ref - 0.2 v ref + 0.2 3.6 0.7 v ccio - 1.1 8 -8 sstl3_ii -0.3 v ref - 0.2 v ref + 0.2 3.6 0.5 v ccio - 0.9 16 -16 sstl15 (ddr3 memory) -0.3 v ref - 0.1 v ref + 0.1 3.6 0.3 v ccio - 0.3 7.5 -7.5 v ccio * 0.8 9 -9 hstl15_i -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 4-4 8-8 hstl18_i -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 8-8 12 -12 hstl18_ii -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 16 -16 1. the average dc current drawn by i/os between gnd connections, or between the last gnd in an i/o bank and the end of an i/o ba nk, as shown in the logic signal connections table shall not exceed n * 8ma, where n is the number of i/os between bank gnd connection s or between the last gnd in a bank and the end of a bank.
3-8 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet sysi/o differential electrical characteristics lv d s 2 5 over recommended operating conditions differential hstl and sstl differential hstl and sstl outputs are implemented as a pair of complementary single-ended outputs. all allow- able single-ended output cl asses (class i and class ii) are supported in this mode. parameter description test conditions min. typ. max. units v inp , v inm input voltage 0 ? 2.4 v v cm input common mode voltage half the sum of the two inputs 0.05 ? 2.35 v v thd differential input threshold differ ence between the two inputs +/-100 ? ? mv i in input current power on or power off ? ? +/-10 a v oh output high voltage for v op or v om r t = 100 ohm ? 1.38 1.60 v v ol output low voltage for v op or v om r t = 100 ohm 0.9v 1.03 ? v v od output voltage differential (v op - v om ), r t = 100 ohm 250 350 450 mv ? v od change in v od between high and low ??50mv v os output voltage offset (v op + v om )/2, r t = 100 ohm 1.125 1.20 1.375 v ? v os change in v os between h and l ? ? 50 mv i sab output short circuit current v od = 0v driver outputs shorted to each other ??12ma
3-9 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet lvds25e the top and bottom sides of latticeecp3 devices support lvds outputs via emulated complementary lvcmos outputs in conjunction with a parallel resistor across the driver outputs. the scheme shown in figure 3-1 is one possible solution for point-to-point signals. figure 3-1. lvds25e output termination example table 3-1. lvds25e dc conditions lvcmos33d all i/o banks support emulated differential i/o using the lvcmos33d i/o type. this option, along with the external resistor network, provides the system designer the flexibility to place differential outputs on an i/o bank with 3.3v v ccio . the default drive current for lvcmos33d output is 12ma with the option to change the device strength to 4ma, 8ma, 16ma or 20ma. follow the lvcmos33 specifications for the dc characteristics of the lvcmos33d. parameter description typical units v ccio output driver supply (+/-5%) 2.50 v z out driver impedance 20 ? r s driver series resistor (+/-1%) 158 ? r p driver parallel resistor (+/-1%) 140 ? r t receiver termination (+/-1%) 100 ? v oh output high voltage 1.43 v v ol output low voltage 1.07 v v od output differential voltage 0.35 v v cm output common mode voltage 1.25 v z back back impedance 100.5 ? i dc dc output current 6.03 ma + - rs=158 ohms (1%) rs=158 ohms (1%) rp = 140 ohms (1%) rt = 100 ohms (1%) off-chip transmission line, zo = 100 ohm differential vccio = 2.5v (5%) 8 ma vccio = 2.5v (5%) on-chip off-chip on-chip 8 ma
3-10 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet blvds25 the latticeecp3 devices support the blvds standard. this standard is emulated using complementary lvcmos outputs in conjunction with a parallel external resistor across the driver outputs. blvds is intended for use when multi-drop and bi-directional multi-point differential signaling is required. the scheme shown in figure 3-2 is one possible solution for bi-directional multi-point differential signals. figure 3-2. blvds25 multi-point output example table 3-2. blvds25 dc conditions 1 over recommended operating conditions parameter description typical units zo = 45 ? zo = 90 ? v ccio output driver supply (+/- 5%) 2.50 2.50 v z out driver impedance 10.00 10.00 ? r s driver series resistor (+/- 1%) 90.00 90.00 ? r tl driver parallel resistor (+/- 1%) 45.00 90.00 ? r tr receiver termination (+/- 1%) 45.00 90.00 ? v oh output high voltage 1.38 1.48 v v ol output low voltage 1.12 1.02 v v od output differentia l voltage 0.25 0.46 v v cm output common mode voltage 1.25 1.25 v i dc dc output current 11.24 10.20 ma 1. for input buffer, see lvds table. heavily loaded backplane, effective zo ~ 45 to 90 ohms differential 2.5v r tl r tr r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms 45-90 ohms 45-90 ohms 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v + - . . . + - . . . + - + - 16ma 16ma 16ma 16ma 16ma 16ma 16ma 16ma
3-11 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet lvpecl33 the latticeecp3 devices support the differential lvpecl standard. this sta ndard is emulated using complemen- tary lvcmos outputs in conj unction with a parallel resistor across the driver outputs. the lvpecl input standard is supported by the lvds differential input buffer. the scheme shown in figure 3-3 is one possible solution for point-to-point signals. figure 3-3. diff erential lvpecl33 table 3-3. lvpec l33 dc conditions 1 over recommended operating conditions parameter description typical units v ccio output driver supply (+/-5%) 3.30 v z out driver impedance 10 ? r s driver series resistor (+/-1%) 93 ? r p driver parallel resistor (+/-1%) 196 ? r t receiver termination (+/-1%) 100 ? v oh output high voltage 2.05 v v ol output low voltage 1.25 v v od output differential voltage 0.80 v v cm output common mode voltage 1.65 v z back back impedance 100.5 ? i dc dc output current 12.11 ma 1. for input buffer, see lvds table. transmission line, zo = 100 ohm differential off-chip on-chip v ccio = 3.3v (+/-5%) v ccio = 3.3v (+/-5%) r p = 196 ohms (+/-1%) r t = 100 ohms (+/-1%) r s = 93.1 ohms (+/-1%) r s = 93.1 ohms (+/-1%) 16ma 16ma + - off-chip on-chip
3-12 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet rsds25e the latticeecp3 devices support differential rsds and rs dse standards. this standard is emulated using com- plementary lvcmos outputs in conjunction with a parallel resistor across the driver outputs. the rsds input stan- dard is supported by the lvds differential input buffer. th e scheme shown in figure 3-4 is one possible solution for rsds standard implementation. resistor values in figure 3-4 are industry standard values for 1% resistors. figure 3-4. rsds25e (reduced swing differential signaling) table 3-4. rsds25e dc conditions 1 over recommended operating conditions parameter description typical units v ccio output driver supply (+/-5%) 2.50 v z out driver impedance 20 ? r s driver series resistor (+/-1%) 294 ? r p driver parallel resistor (+/-1%) 121 ? r t receiver termination (+/-1%) 100 ? v oh output high voltage 1.35 v v ol output low voltage 1.15 v v od output differential voltage 0.20 v v cm output common mode voltage 1.25 v z back back impedance 101.5 ? i dc dc output current 3.66 ma 1. for input buffer, see lvds table. r s = 294 ohms (+/-1%) r s = 294 ohms (+/-1%) r p = 121 ohms (+/-1%) r t = 100 ohms (+/-1%) on-chip on-chip 8ma 8ma v ccio = 2.5v (+/-5%) v ccio = 2.5v (+/-5%) transmission line, zo = 100 ohm differential + - off-chip off-chip
3-13 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet mlvds25 the latticeecp3 devices support the differential mlvds standard. this standard is emulated using complemen- tary lvcmos outputs in conjunction with a parallel resistor across the driver outputs. the mlvds input standard is supported by the lvds differential input buffer. the scheme shown in figure 3-5 is one possible solution for mlvds standard implementation. resistor values in figure 3-5 are industry standard values for 1% resistors. figure 3-5. mlvds25 (multipoint low voltage differential signaling) table 3-5. mlvds25 dc conditions 1 parameter description typical units zo=50 ? zo=70 ? v ccio output driver supply (+/-5%) 2.50 2.50 v z out driver impedance 10.00 10.00 ? r s driver series resistor (+/-1%) 35.00 35.00 ? r tl driver parallel resistor (+/-1%) 50.00 70.00 ? r tr receiver termination (+/-1%) 50.00 70.00 ? v oh output high voltage 1.52 1.60 v v ol output low voltage 0.98 0.90 v v od output differential voltage 0.54 0.70 v v cm output common mode voltage 1.25 1.25 v i dc dc output current 21.74 20.00 ma 1. for input buffer, see lvds table. 16ma 2.5v + - 2.5v 2.5v + - 2.5v 2.5v + - a m 6 1 heavily loaded backplace, effective zo~50 to 70 ohms differential 50 to 70 ohms +/-1% r s = 35ohms r s = 35ohms r s = 35ohms r s = 35ohms r s = 35ohms r s = 35ohms r s = 35ohms r tr r tl 16ma 2.5v a m 6 1 2.5v + - a m 6 1 2.5v 2.5v r s = 50 to 70 ohms +/-1% 35ohms a m 6 1 16ma + - 16ma oe oe oe oe oe oe oe oe
3-14 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet typical building block function performance pin-to-pin performance (lvcmos25 12ma drive) 1, 2 function -8 timing units basic functions 16-bit decoder 4.7 ns 32-bit decoder 4.7 ns 64-bit decoder 5.7 ns 4:1 mux 4.1 ns 8:1 mux 4.3 ns 16:1 mux 4.7 ns 32:1 mux 4.8 ns 1. these functions were generated using the isplever design tool. ex act performance may vary with device and tool version. the tool uses internal parameters that have been characterized but are not tested on every device. 2. commercial timing numbers are shown. industrial numbers are ty pically slower and can be extracted from the isplever software. register-to-register performance 1, 2 function -8 timing units basic functions 16-bit decoder 500 mhz 32-bit decoder 500 mhz 64-bit decoder 475 mhz 4:1 mux 500 mhz 8:1 mux 500 mhz 16:1 mux 500 mhz 32:1 mux 445 mhz 8-bit adder 500 mhz 16-bit adder 500 mhz 64-bit adder 305 mhz 16-bit counter 500 mhz 32-bit counter 460 mhz 64-bit counter 320 mhz 64-bit accumulator 315 mhz embedded memory functions 512x36 single port ram, eb r output registers 340 mhz 1024x18 true-dual port ram (write through or normal, ebr output registers) 340 mhz 1024x18 true-dual port ram (read-before-write, ebr output registers; ea devices only) 130 mhz 1024x18 true-dual port ram (write through or normal, plc output registers) 245 mhz distributed memory functions 16x4 pseudo-dual port ram (one pfu) 500 mhz 32x4 pseudo-dual port ram 500 mhz 64x8 pseudo-dual port ram 380 mhz dsp function 18x18 multiplier (all registers) 400 mhz 9x9 multiplier (all registers) 400 mhz 36x36 multiply (all registers) 245 mhz
3-15 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet , 2 derating timing tables logic timing provided in the following sections of this data sheet and the isplever design tools are worst case numbers in the operating range. actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. the isplever design tool can provide logic timing numbers at a particular temperature and voltage. 18x18 multiply/accumulate (input & output registers) 200 mhz 18x18 multiply-add/sub (all registers) 400 mhz dsp ip functions 16-tap fully-parallel fir filter mhz 1024-pt, radix 4, decimation in frequency fft mhz 8x8 matrix multiplication mhz 1. these timing numbers were generated using is plever tool. exact performance may vary with device and tool version. the tool u ses inter- nal parameters that have been characterized but are not tested on every device. 2. commercial timing numbers are shown. industrial numbers are ty pically slower and can be extracted from the isplever software. register-to-register performance 1, 2 function -8 timing units
3-16 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet latticeecp3 external switching characteristics 1, 2 over recommended commercial operating conditions parameter description device -8 -7 -6 units min. max. min. max. min. max. clocks primary clock 6 f max_pri frequency for primary clock tree ecp3-150ea ? 500 ? 420 ? 375 mhz t w_pri clock pulse width for primary clock ecp3-150ea 0.8 ? 0.9 ? 1.0 ? ns t skew_pri primary clock skew within a device ecp3-150ea ? 300 ? 330 ? 360 ps t skew_prib primary clock skew within a bank ecp3-150ea ? 250 ? 280 ? 300 ps f max_pri frequency for primary clock tree ecp3-70e/95e ? 500 ? 420 ? 375 mhz f max_pri frequency for primary clock tree ecp3-70e/95e 0.8 ? 0.9 ? 1.0 ? ns t skew_pri primary clock skew within a device ecp3-70e/95e ? 300 ? 330 ? 360 ps t skew_prib primary clock skew within a bank ecp3-70e/95e ? 250 ? 280 ? 300 ps edge clock 6 f max_edge frequency for edge clock ecp3-150ea ? 500 ? 420 ? 375 mhz t w_edge clock pulse width for edge clock ecp3-150ea 0.9 ? 1.0 ? 1.2 ? ns t skew_edge_dqs edge clock skew within an edge of the device ecp3-150ea ? 200 ? 210 ? 220 ps f max_edge frequency for edge clock ecp3-70e/95e ? 500 ? 420 ? 375 mhz t w_edge clock pulse width for edge clock ecp3-70e/95e 0.9 ? 1.0 ? 1.2 ? ns t skew_edge_dqs edge clock skew within an edge of the device ecp3-70e/95e ? 200 ? 225 ? 250 ps parameter description device -8 -7 -6 units min. max. min. max. min. max. generic sdr general i/o pin parameters using dedicated clock input primary clock without pll 2 t co clock to output - pio output register ecp3-150ea ? 4.0 ? 4.4 ? 4.8 ns t su clock to data setup - pio input regis- ter ecp3-150ea 0.0 ? 0.0 ? 0.0 ? ns t h clock to data hold - pio input regis- ter ecp3-150ea 1.6 ? 1.8 ? 2.1 ? ns t su_del clock to data setup - pio input regis- ter with data input delay ecp3-150ea 1.2 ? 1.3 ? 1.5 ? ns t h_del clock to data hold - pio input regis- ter with input data delay ecp3-150ea 0.1 ? 0.1 ? 0.1 ? ns f max_io clock frequency of i/o and pfu reg- ister ecp3-150ea ? 500 ? 420 ? 375 mhz t co clock to output - pio output register ecp3-70e/95e ? 3.9 ? 4.3 -? 4.7 ns t su clock to data setup - pio input regis- ter ecp3-70e/95e 0.0 ? 0.0 ? 0.0 ? ns t h clock to data hold - pio input regis- ter ecp3-70e/95e 1.5 ? 1.8 ? 2.0 ? ns t su_del clock to data setup - pio input regis- ter with data input delay ecp3-70e/95e 1.3 ? 1.5 ? 1.8 ? ns t h_del clock to data hold - pio input regis- ter with input data delay ecp3-70e/95e 0.0 ? 0.0 ? 0.0 ? ns
3-17 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet f max_io clock frequency of i/o and pfu reg- ister ecp3-70e/95e ? 500 ? 420 ? 375 mhz general i/o pin parameters using dedicated clock input pr imary clock with pll with clock injection removal setting 2 t copll clock to output - pio output register ecp3-150ea ? 2.5 ? 2.7 ? 3.1 ns t supll clock to data setup - pio input regis- ter ecp3-150ea 0.6 ? 0.6 ? 0.7 ? ns t hpll clock to data hold - pio input regis- ter ecp3-150ea 0.9 ? 1.0 ? 1.1 ? ns t su_delpll clock to data setup - pio input regis- ter with data input delay ecp3-150ea 1.5 ? 1.6 ? 1.8 ? ns t h_delpll clock to data hold - pio input regis- ter with input data delay ecp3-150ea ? 0.1 ? 0.1 ? 0.1 ns t copll clock to output - pio output register ecp3-70e/95e ? 2.2 ? 2.3 ? 2.5 ns t supll clock to data setup - pio input regis- ter ecp3-70e/95e 0.6 ? 0.7 ? 0.8 ? ns t hpll clock to data hold - pio input regis- ter ecp3-70e/95e 0.9 ? 1.1 ? 1.3 ? ns t su_delpll clock to data setup - pio input regis- ter with data input delay ecp3-70e/95e 1.6 ? 1.9 ? 2.1 ? ns t h_delpll clock to data hold - pio input regis- ter with input data delay ecp3-70e/95e 0.0 ? 0.0 ? 0.0 ? ns parameter description device -8 -7 -6 units min. max. min. max. min. max. generic ddr generic ddrx1 inputs with cl ock and data (>10 bits wide) centered at pin (gddrx1_rx.sclk.ce ntered) using pclk pin for clock input data left, right and top sides & clock left, right and top sides t sugddr data setup before clk ecp3-150ea ? ? ? ps t hgddr data hold after clk ecp3-150ea ? ? ? ps f max_gddr ddrx1 clock frequency ecp3-150ea ? ? ? mhz generic ddrx1 inputs with clock in the center of data window, wi thout dll (gddrx1_rx.eclk.centered) t sugddr data setup before clk ecp3-70e/95e 515 ? 515 ? 515 ? ps t hogddr data hold after clk ecp3-70e/95e 515 ? 515 ? 515 ? ps f max_gddr ddrx1 clock frequency ecp3-70e/95e ? 250 ? 250 ? 250 mhz generic ddrx1 inputs with clock and da ta (> 10 bits wide) al igned at pin (gddrx1_rx.sclk.aligned) using dll- clkin pin for clock input data left, right and top sides & clock left and right sides t dvaclkgddr data setup before clk ecp3-150ea ? ? ? ui t dveclkgddr data hold after clk ecp3-150ea ? ? ? ui f max_gddr ddrx1 clock frequency ecp3-150ea ? ? ? mhz generic ddrx1 inputs with clock and data a ligned, with dll (gd drx1_rx.eclk.aligned) t dvaclkgddr data setup before clk ecp3-70e/95e ? 0.235 ? 0.235 ? 0.235 ui t dveclkgddr data hold after clk ecp3-70e/95e 0.765 ? 0.765 ? 0.765 ? ui latticeecp3 external switching characteristics (continued) 1, 2 over recommended commercial operating conditions parameter description device -8 -7 -6 units min. max. min. max. min. max.
3-18 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet f max_gddr ddrx1 clock frequency ecp3-70e/95e ? 250 ? 250 ? 250 mhz generic ddrx1 inputs with clock and da ta (<10 bits wide) centered at pi n (gddrx1_rx.dqs.centered) using dqs pin for clock input left, right and top for data and clock t sugddr data valid after clk ecp3-150ea ? ? ? ns t hgddr data hold after clk ecp3-150ea ? ? ? ns f max_gddr ddrx1 clock frequency ecp3-150ea ? ? ? ns generic ddrx1 inputs with clock and da ta (<10 bits wide) aligned at pin (gddrx1_rx.dqs.aligned) using dqs pin for clock input left and right sides t dvaclkgddr data setup before clk (left and right sides) ecp3-150ea ? ? ? ui t dveclkgddr data hold after clk (left and right sides) ecp3-150ea ? ? ? ui f max_gddr ddrx1 clock frequency (left and right sides) ecp3-150ea ? ? ? ui top side t dvaclkgddr data setup before clk (top side) ecp3-150ea ? ? ? ui t dveclkgddr data hold after clk (top side) ecp3-150ea ? ? ? ui f max_gddr ddrx1 clock frequency (top side) ecp3-150ea ? ? ? ui generic ddrx2 inputs with cl ock and data (>10 bits wide) centered at pin (gddrx2_rx.eclk.ce ntered) using pclk pin for clock input left and right sides t sugddr data setup before clk ecp3-150ea ? ? ? ns t hgddr data hold after clk ecp3-150ea ? ? ? ns f max_gddr ddrx2 clock frequency ecp3-150ea ? ? ? mhz generic ddrx2 inputs with clock in the center of data window, without dll 3 (gddrx2_rx.eclk.centered) t sugddr data setup before clk ecp3-70e/95e 260 ? 312 ? 352 ? ps t hogddr data hold after clk ecp3-70e/95e 260 ? 312 ? 352 ? ps f max_gddr ddr/ddrx2 clock frequency 8 ecp3-70e/95e ? 500 ? 420 ? 375 mhz generic ddrx2 inputs with clock and data (>10 bits wide) aligned at pin (gddrx2_rx.eclk.aligned) left and right side using dllclkin pin for clock input t dvaclkgddr data setup before clk (left and right side) ecp3-150ea ? ? ? ui t dveclkgddr data hold after clk (left and right side) ecp3-150ea ? ? ? ui f max_gddr ddrx1 clock frequency (left and right side) ecp3-150ea ? ? ? mhz top side using pclk pin for clock input t dvaclkgddr data setup before clk (top side) ecp3-150ea ? ? ? ui t dveclkgddr data hold after clk (top side) ecp3-150ea ? ? ? ui f max_gddr ddrx1 clock frequency (top side) ecp3-150ea ? ? ? mhz generic ddrx2 inputs with clock and data edges aligned, with dlldel 3 (gddrx2_rx.eclk.aligned) t dvaclkgddr data valid after clk ecp3-70e/95e ? 0.235 ? 0.235 ? 0.235 ui latticeecp3 external switching characteristics (continued) 1, 2 over recommended commercial operating conditions parameter description device -8 -7 -6 units min. max. min. max. min. max.
3-19 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet t dveclkgddr data hold after clk ecp3-70e/95e 0.765 ? 0.765 ? 0.765 ? ui f max_gddr ddr/ddrx2 clock frequency 8 ecp3-70e/95e ? 500 ? 420 ? 375 mhz generic ddrx2 inputs with clock and da ta (<10 bits wide) centered at pi n (gddrx2_rx.dqs.centered) using dqs pin for clock input left and right sides t sugddr data setup before clk ecp3-150ea ? ? ? ns t hgddr data hold after clk ecp3-150ea ? ? ? ns f max_gddr ddrx2 clock frequency ecp3-150ea ? ? ? ns generic ddrx2 inputs with clock and da ta (<10 bits side) aligned at pin (g ddrx2_rx.dqs.aligned) using dqs pin for clock input left and right sides t dvaclkgddr data setup before clk (left and right side) ecp3-150ea ? ? ? t dveclkgddr data hold after clk (left and right side) ecp3-150ea ? ? ? f max_gddr ddrx2 clock frequency (left and right side) ecp3-150ea ? ? ? generic ddrx1 output with clock and data (>10 bits wide) centered at pin (gddrx1_tx.sclk.centered) left, right and top sides t dvbgddr data valid before clk ecp3-150ea ? ? ? t dvagddr data valid after clk ecp3-150ea ? ? ? f max_gddr ddrx1 clock frequency ecp3-150ea ? ? ? generic ddrx1 outputs with clock in the center of data window, with pll 90-degree shifted clock ouput (gddrx1_tx.eclk.centered) t dibgddr data invalid before clk ecp3-70e/95e 670 ? 670 ? 670 ? ps t diagddr data invalid after clk ecp3-70e/95e 670 ? 670 ? 670 ? ps fmax_gddr ddrx1 clock frequency ecp3-70e/95e ? 250 ? 250 ? 250 mhz generic ddrx1 output with clock and data (> 10 bi ts wide) aligned at pi n (gddrx1_tx.sclk.aligned) left, right and top sides t dibgddr data hold after clk ecp3-150ea ? ? ? t diagddr data setup before clk ecp3-150ea ? ? ? f max_gddr ddrx1 clock frequency ecp3-150ea ? ? ? generic ddrx1 outputs with clock and data edge aligned, without pll t dibgddr data invalid before clk ecp3-70e/95e ? 330 ? 330 ? 330 ps t diagddr data invalid after clk ecp3-70e/95e ? 330 ? 330 ? 330 ps f max_gddr ddrx1 clock frequency ecp3-70e/95e ? 250 ? 250 ? 250 mhz generic ddrx1 output with clock and data (<10 bits wide) centered at pin (gddrx1_tx.dqs.centered) left, right and top sides t dvbgddr data valid before clk ecp3-150ea ? ? ? t dvagddr data valid after clk ecp3-150ea ? ? ? f max_gddr ddrx1 clock frequency ecp3-150ea ? ? ? latticeecp3 external switching characteristics (continued) 1, 2 over recommended commercial operating conditions parameter description device -8 -7 -6 units min. max. min. max. min. max.
3-20 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet generic ddrx2 output with clock and data (> 10 bi ts wide) aligned at pi n (gddrx2_tx.eclk.aligned) left and right sides t dibgddr data setup before clk ecp3-150ea ? ? ? ps t diagddr data hold after clk ecp3-150ea ? ? ? ps f max_gddr ddrx2 clock frequency ecp3-150ea ? ? ? mhz generic ddrx2 outputs with clock an d data edges aligned, without pll 90-degre e shifted clock output 5 (gddrx2_tx.aligned) t dibgddr data invalid before clock ecp3-70e/95e ? 200 ? 225 ? 250 ps t diagddr data invalid after clock ecp3-70e/95e ? 200 ? 225 ? 250 ps f max_gddr ddr/ddrx2 clock frequency 8 ecp3-70e/95e ? 500 ? 420 ? 375 mhz generic ddrx2 output with clock and data (> 10 bits wide) centered at pin using dqsdll (gddrx2_tx.dqs- dll.centered) left and right sides t dvbgddr data valid before clk ecp3-150ea ? ? ? ns t dvagddr data valid after clk ecp3-150ea ? ? ? ns f max_gddr ddrx2 clock frequency ecp3-150ea ? ? ? ns generic ddrx2 output with clock and da ta (> 10 bits wide) centered at pi n using pll (gddrx2_tx.pll.centered) left and right sides t dvbgddr data valid before clk ecp3-150ea ? ? ? ns t dvagddr data valid after clk ecp3-150ea ? ? ? ns f max_gddr ddrx2 clock frequency ecp3-150ea ? ? ? ns generic ddrx2 outputs with clock edge in the center of data window, wi th pll 90-degree shifted clock output 6 (gddrx2_tx.pll.centered) t dvbgddr data valid before clk ecp3-70e/95e 300 ? 370 ? 417 ? ps t dvagddr data valid after clk ecp3-70e/95e 300 ? 370 ? 417 ? ps f max_gddr ddr/ddrx2 clock frequency 8 ecp3-70e/95e ? 500 ? 420 ? 375 mhz parameter description device -8 -7 -6 units min. max. min. max. min. max. memory interface ddr/ddr2 sdram i/o pin parameters (input data are strobe edge aligned, output strobe edge is data centered) 4 t dvadq data valid after dqs (ddr read) ecp3-150ea ? 0.225 ? 0.225 ? 0.225 ui t dvedq data hold after dqs (ddr read) ecp3-150ea 0.64 ? 0.64 ? 0.64 ? ui t dqvbs data valid before dqs ecp3-150ea 0.25 ? 0.25 ? 0.25 ? ui t dqvas data valid after dqs ecp3-150ea 0.25 ? 0.25 ? 0.25 ? ui f max_ddr ddr clock frequency ecp3-150ea 95 200 95 200 95 166 mhz f max_ddr2 ddr2 clock frequency ecp3-150ea 133 266 133 200 133 166 mhz t dvadq data valid after dqs (ddr read) ecp3-70e/95e ? 0.225 ? 0.225 ? 0.225 ui t dvedq data hold after dqs (ddr read) ecp3-70e/95e 0.64 ? 0.64 ? 0.64 ? ui t dqvbs data valid before dqs ecp3-70e/95e 0.25 ? 0.25 ? 0.25 ? ui t dqvas data valid after dqs ecp3-70e/95e 0.25 ? 0.25 ? 0.25 ? ui f max_ddr ddr clock frequency ecp3-70e/95e 95 200 95 200 95 133 mhz latticeecp3 external switching characteristics (continued) 1, 2 over recommended commercial operating conditions parameter description device -8 -7 -6 units min. max. min. max. min. max.
3-21 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet f max_ddr2 ddr2 clock frequency ecp3-70e/95e 133 266 133 200 133 166 mhz ddr3 (using pll for sclk) i/o pin parameters t dvadq data valid after dqs (ddr read) ecp3-150ea ? 0.225 ? 0.225 ? 0.225 ui t dvedq data hold after dqs (ddr read) ecp3-150ea 0.64 ? 0.64 ? 0.64 ? ui t dqvbs data valid before dqs ecp3-150ea 0.25 ? 0.25 ? 0.25 ? ui t dqvas data valid after dqs ecp3-150ea 0.25 ? 0.25 ? 0.25 ? ui f max_ddr3 ddr3 clock frequency ecp3-150ea 266 400 266 333 266 300 mhz 1. commercial timing numbers are shown. industrial numbers are typically slower and can be extracted from the isplever software. 2. general i/o timing numbers based on lvcmos 2.5, 12ma, 0pf load. 3. generic ddr timing numbers based on lvds i/o. 4. ddr timing numbers based on sstl25. ddr2 timing numbers based on sstl18. 5. ddr3 timing numbers based on sstl15. 6. uses lvds i/o standard. 7. the current version of software does not support per bank skew numbers; this will be supported in a future release. 8. maximum clock frequencies are tested under best case conditions. system performance may vary upon the user environment. latticeecp3 external switching characteristics (continued) 1, 2 over recommended commercial operating conditions parameter description device -8 -7 -6 units min. max. min. max. min. max.
3-22 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet figure 3-6. generic ddr/ddr2 (with clock and data edges aligned) t t t t t t t t clk rdtclk data (rdat, rctl) data (tdat, tctl) dibgddr dibgddr dvaclkgddr dvaclkgddr dveclkgddr dveclkgddr diagddr diagddr transmit parameters receive parameters
3-23 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet figure 3-7. ddr/ddr2/ddr3 sdram figure 3-8. generic ddr/ ddr2 parameters (with clock center on data window) transmit parameters dqs dqs dq dq receive parameters t dqvbs t dvadq t dvedq t dvedq t dvadq t dqvas t dqvas t dqvbs t t t t t t t t dvbckgddr dvackgddr hgddr hgddr sugddr sugddr dvackgddr dvbckgddr transmit parameters clock clock data data receive parameters
3-24 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet latticeecp3 internal sw itching characteristics 1, 2 over recommended commercial operating conditions parameter description -8 -7 -6 units. min. max. min. max. min. max. pfu/pff logic mode timing t lut4_pfu lut4 delay (a to d inputs to f output) ? 0.147 ? 0.163 ? 0.179 ns t lut6_pfu lut6 delay (a to d inputs to ofx output) ? 0.273 ? 0.307 ? 0.342 ns t lsr_pfu set/reset to output of pfu (asynchronus) ? 0.593 ? 0.674 ? 0.756 ns t lsrrec_pfu asynchronous set/reset recovery time for pfu logic ?0.298?0.345?0.391ns t sum_pfu clock to mux (m0,m1) input setup time 0.134 ? 0.144 ? 0.153 ? ns t hm_pfu clock to mux (m0,m1) input hold time -0.097 ? -0.103 ? -0.109 ? ns t sud_pfu clock to d input setup time 0.061 ? 0.068 ? 0.075 ? ns t hd_pfu clock to d input hold time 0.019 ? 0.013 ? 0.015 ? ns t ck2q_pfu clock to q delay, (d-type register ? configuration) ?0.243?0.273?0.303ns pfu dual port memory mode timing t coram_pfu clock to output (f port) ? 0.710 ? 0.803 ? 0.897 ns t sudata_pfu data setup time -0.137 ? -0.155 ? -0.174 ? ns t hdata_pfu data hold time 0.188 ? 0.217 ? 0.246 ? ns t suaddr_pfu address setup time -0.227 ? -0.257 ? -0.286 ? ns t haddr_pfu address hold time 0.240 ? 0.275 ? 0.310 ? ns t suwren_pfu write/read enable setup time -0.055 ? -0.055 ? -0.063 ? ns t hwren_pfu write/read enable hold time 0.059 ? 0.059 ? 0.071 ? ns pic timing pio input/output buffer timing t in_pio input buffer delay (lvcmos25) ? 0.423 ? 0.466 ? 0.508 ns t out_pio output buffer delay (lvcmos25) ? 1.115 ? 1.155 ? 1.196 ns iologic input/output timing t sui_pio input register setup time (data before clock) 0.956 ? 1.124 ? 1.293 ? ns t hi_pio input register hold time (data after clock) 0.313 ? 0.395 ? 0.378 ? ns t coo_pio output register clock to output delay 4 ?1.455?1.564?1.674ns t suce_pio input register clock enable setup time 0.220 ? 0.185 ? 0.150 ? ns t hce_pio input register clock enable hold time -0.085 ? -0.072 ? -0.058 ? ns t sulsr_pio set/reset setup time 0.117 ? 0.103 ? 0.088 ? ns t hlsr_pio set/reset hold time -0.107 ? -0.094 ? -0.081 ? ns ebr timing t co_ebr clock (read) to output from address or data ? 2.78 ? 2.89 ? 2.99 ns t coo_ebr clock (write) to output from ebr output reg- ister ? 0.31 ? 0.32 ? 0.33 ns t sudata_ebr setup data to ebr memory -0.218 ? -0.227 ? -0.237 ? ns t hdata_ebr hold data to ebr memory 0.249 ? 0.257 ? 0.265 ? ns t suaddr_ebr setup address to ebr memroy -0.071 ? -0.070 ? -0.068 ? ns t haddr_ebr hold address to ebr memory 0.118 ? 0.098 ? 0.077 ? ns t suwren_ebr setup write/read enable to pfu memory -0.107 ? -0.106 ? -0.106 ? ns
3-25 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet t hwren_ebr hold write/read enable to pfu memory 0.141 ? 0.145 ? 0.149 ? ns t suce_ebr clock enable setup ti me to ebr output register 0.087 0.096 0.104 ns t hce_ebr clock enable hold time to ebr output register -0.066 -0.080 -0.094 ns t sube_ebr byte enable set-up time to ebr output register -0.071 -0.070 -0.068 ns t hbe_ebr byte enable hold time to ebr output register 0.118 0.098 0.077 ns dsp block timing 3 t sui_dsp input register setup time 0.32 ? 0.36 ? 0.39 ? ns t hi_dsp input register hold time -0.17 ? -0.19 ? -0.21 ? ns t sup_dsp pipeline register setup time 2.23 ? 2.30 ? 2.37 ? ns t hp_dsp pipeline register hold time -1.02 ? -1.09 ? -1.15 ? ns t suo_dsp output register setup time 3.09 ? 3.22 ? 3.34 ? ns t ho_dsp output register hold time -1.67 ? -1.76 ? -1.84 ? ns t coi_dsp input register clock to output time ? 3.68 ? 4.03 ? 4.38 ns t cop_dsp pipeline register clock to output time ? 1.30 ? 1.47 ? 1.64 ns t coo_dsp output register clock to output time ? 0.58 ? 0.60 ? 0.62 ns t suopt_dsp opcode register setup time 0.31 ? 0.35 ? 0.39 ? ns t hopt_dsp opcode register hold time -0.20 ? -0.24 ? -0.27 ? ns t sudata_dsp cascade_data through alu to output register setup time 1.55 ? 1.67 ? 1.78 ? ns t hpdata_dsp cascade_data through alu to output register hold time -0.44 ? -0.53 ? -0.61 ? ns 1. internal parameters are characteri zed but not tested on every device. 2. commercial timing numbers are shown. industrial timing numbers are typically slower and can be extracted from the isplever so ftware. 3. dsp slice is configured in multiply add/sub 18x18 mode. 4. the output register is in flip-flop mode. latticeecp3 internal sw itching characteristics 1, 2 (continued) over recommended commercial operating conditions parameter description -8 -7 -6 units. min. max. min. max. min. max.
3-26 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet timing diagrams figure 3-9. read/write mode (normal) note: input data and address are registered at the positive edge of the clock and output data appears after the positive edge o f the clock. figure 3-10. read/write mode with input and output registers a0 a1 a0 a1 d0 d1 doa a0 t co_ebr t co_ebr t co_ebr t su t h d0 d1 d0 dia ada wea csa clka a0 a1 a0 a0 d0 d1 output is only updated during a read cycle a1 d0 d1 mem(n) data from previous read dia ada wea csa clka doa (regs) t su t h t coo_ebr t coo_ebr
3-27 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet figure 3-11. write through (sp read/wri te on port a, input registers only) note: input data and address are registered at the positive edge of the clock and output data appears after the positive edge o f the clock. a0 a1 a0 d0 d1 d4 t su t access t access t access t h d2 d3 d4 d0 d1 d2 data from prev read or write three consecutive writes to a0 d3 doa dia ada wea csa clka t access
3-28 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet latticeecp3 family timing adders 1, 2, 3, 4, 5 over recommended commercial operating conditions buffer type description -8 -7 -6 units input adjusters lvds25e lvds, emulated, vccio = 2.5v 0.03 -0.01 -0.03 ns lvds25 lvds, vccio = 2.5v 0.03 0.00 -0.04 ns blvds25 blvds, emulated, vccio = 2.5v 0.03 0.00 -0.04 ns mlvds25 mlvds, emulated, vccio = 2.5v 0.03 0.00 -0.04 ns rsds25 rsds, vccio = 2.5v 0.03 0.00 -0.03 ns pplvds point-to-point lvds 0.03 -0.01 -0.03 ns trlvds transition-reduced lvds 0.03 0.00 -0.04 ns mini mlvds mini lvds 0.03 -0.01 -0.03 ns lvpecl33 lvpecl, emulated, vc cio = 3.0v 0.17 0.07 -0.04 ns hstl18_i hstl_18 class i, vccio = 1.8v 0. 20 0.17 0.13 ns hstl18_ii hstl_18 class ii, vccio = 1.8v 0.20 0.17 0.13 ns hstl18d_i differential hstl 18 class i 0.20 0.17 0.13 ns hstl18d_ii differential hstl 18 class ii 0.20 0.17 0.13 ns hstl15_i hstl_15 class i, vccio = 1.5v 0. 10 0.12 0.13 ns hstl15d_i differential hstl 15 class i 0.10 0.12 0.13 ns sstl33_i sstl_3 class i, vccio = 3.0v 0.17 0.23 0.28 ns sstl33_ii sstl_3 class ii, v ccio = 3.0v 0.17 0.23 0.28 ns sstl33d_i differential sstl_3 class i 0.17 0.23 0.28 ns sstl33d_ii differential sstl_3 class ii 0.17 0.23 0.28 ns sstl25_i sstl_2 class i, vccio = 2.5v 0.12 0.14 0.16 ns sstl25_ii sstl_2 class ii, v ccio = 2.5v 0.12 0.14 0.16 ns sstl25d_i differential sstl_2 class i 0.12 0.14 0.16 ns sstl25d_ii differential sstl_2 class ii 0.12 0.14 0.16 ns sstl18_i sstl_18 class i, vc cio = 1.8v 0.08 0.06 0.04 ns sstl18_ii sstl_18 class ii, v ccio = 1.8v 0.08 0.06 0.04 ns sstl18d_i differential sstl_18 class i 0.08 0.06 0.04 ns sstl18d_ii differential sstl_1 8 class ii 0.08 0.06 0.04 ns sstl15 sstl_15, vccio = 1.5v 0.087 0.059 0.032 ns sstl15d differential sstl_15 0.087 0.025 -0.036 ns lvttl33 lvttl, vccio = 3.0v 0.05 0.05 0.05 ns lvcmos33 lvcmos, vccio = 3.0v 0.05 0.05 0.05 ns lvcmos25 lvcmos, vccio = 2.5v 0.00 0.00 0.00 ns lvcmos18 lvcmos, vccio = 1.8v 0.06 0.08 0.11 ns lvcmos15 lvcmos, vccio = 1.5v 0.17 0.21 0.25 ns lvcmos12 lvcmos, vccio = 1.2v 0.01 0.05 0.08 ns pci33 pci, vccio = 3.0v 0.05 0.05 0.05 ns output adjusters lvds25e lvds, emulated, vccio = 2.5v 0.15 0.15 0.16 ns lvds25 lvds, vccio = 2.5v 0.02 0.08 0.13 ns blvds25 blvds, emulated, vccio = 2.5v 0.00 -0.02 -0.04 ns mlvds25 mlvds, emulated, vccio = 2.5v 0.00 -0.01 -0.03 ns
3-29 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet rsds25 rsds, vccio = 2.5v 0.05 0.10 0.16 ns pplvds point-to-point lvds, emulated, vccio = 2.5v -0.10 -0.05 0.01 ns lvpecl33 lvpecl, emulated, vcci o = 3.0v -0.02 -0.04 -0.06 ns hstl18_i hstl_18 class i 8ma drive, vccio = 1.8v -0.19 -0.16 -0.12 ns hstl18_ii hstl_18 class ii, vc cio = 1.8v -0.30 -0.28 -0.25 ns hstl18d_i differential hstl 18 class i 8ma drive -0.19 -0.16 -0.12 ns hstl18d_ii differential hstl 18 class ii -0.30 -0.28 -0.25 ns hstl15_i hstl_15 class i 4ma drive, vccio = 1.5v -0.22 -0.19 -0.16 ns hstl15d_i differential hstl 15 class i 4ma drive -0.22 -0.19 -0.16 ns sstl33_i sstl_3 class i, vccio = 3.0v 0.08 0.13 0.19 ns sstl33_ii sstl_3 class ii, vcci o = 3.0v -0.20 -0.17 -0.14 ns sstl33d_i differential sstl_3 class i 0.08 0.13 0.18 ns sstl33d_ii differential sstl_3 class ii -0.20 -0.17 -0.14 ns sstl25_i sstl_2 class i 8ma drive, vccio = 2.5v -0.06 -0.02 0.02 ns sstl25_ii sstl_2 class ii 16ma drive, vccio = 2.5v -0.19 -0.15 -0.12 ns sstl25d_i differential sstl_2 cla ss i 8ma drive -0.06 -0.02 0.02 ns sstl25d_ii differential sstl_2 cla ss ii 16ma drive -0.19 -0.15 -0.12 ns sstl18_i sstl_1.8 class i, vccio = 1.8v -0.14 -0.10 -0.07 ns sstl18_ii sstl_1.8 class ii 8ma driv e, vccio = 1.8v -0.20 -0.17 -0.14 ns sstl18d_i differential sstl_1.8 class i -0.14 -0.10 -0.07 ns sstl18d_ii differential sstl_1.8 cl ass ii 8ma drive -0.20 -0.17 -0.14 ns sstl15 sstl_1.5, vccio = 1.5v 0.07 0.08 0.08 ns sstl15d differential sstl_15 0.07 0.08 0.08 ns lvttl33_4ma lvttl 4ma drive, vccio = 3.0v 0.21 0.23 0.25 ns lvttl33_8ma lvttl 8ma drive, vccio = 3.0v 0.09 0.09 0.10 ns lvttl33_12ma lvttl 12ma drive, vccio = 3.0v 0.02 0.03 0.03 ns lvttl33_16ma lvttl 16ma drive, vccio = 3.0v 0.12 0.13 0.13 ns lvttl33_20ma lvttl 20ma drive, vccio = 3.0v 0.08 0.08 0.09 ns lvcmos33_4ma lvcmos 3.3 4ma drive, fast slew rate 0.21 0.23 0.25 ns lvcmos33_8ma lvcmos 3.3 8ma drive, fast slew rate 0.09 0.09 0.10 ns lvcmos33_12ma lvcmos 3.3 12ma drive, fast slew rate 0.02 0.03 0.03 ns lvcmos33_16ma lvcmos 3.3 16ma drive, fast slew rate 0.12 0.13 0.13 ns lvcmos33_20ma lvcmos 3.3 20ma drive, fast slew rate 0.08 0.08 0.09 ns lvcmos25_4ma lvcmos 2.5 4ma drive, fast slew rate 0.12 0.12 0.12 ns lvcmos25_8ma lvcmos 2.5 8ma drive, fast slew rate 0.05 0.05 0.05 ns lvcmos25_12ma lvcmos 2.5 12ma drive, fast slew rate 0.00 0.00 0.00 ns lvcmos25_16ma lvcmos 2.5 16ma drive, fast slew rate 0.08 0.08 0.08 ns lvcmos25_20ma lvcmos 2.5 20ma drive, fast slew rate 0.04 0.04 0.04 ns lvcmos18_4ma lvcmos 1.8 4ma drive, fast slew rate 0.08 0.09 0.09 ns lvcmos18_8ma lvcmos 1.8 8ma drive, fast slew rate 0.02 0.01 0.01 ns lvcmos18_12ma lvcmos 1.8 12ma drive, fast slew rate -0.03 -0.03 -0.03 ns lvcmos18_16ma lvcmos 1.8 16ma drive, fast slew rate 0.03 0.03 0.03 ns latticeecp3 family timing adders 1, 2, 3, 4, 5 (continued) over recommended commercial operating conditions buffer type description -8 -7 -6 units
3-30 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet lvcmos15_4ma lvcmos 1.5 4ma drive, fast slew rate 0.09 0.10 0.10 ns lvcmos15_8ma lvcmos 1.5 8ma drive, fast slew rate 0.01 0.01 0.00 ns lvcmos12_2ma lvcmos 1.2 2ma drive, fast slew rate 0.08 0.08 0.08 ns lvcmos12_6ma lvcmos 1.2 6ma drive, fast slew rate -0.02 -0.02 -0.02 ns lvcmos33_4ma lvcmos 3.3 4ma drive, slow slew rate 1.64 1.71 1.77 ns lvcmos33_8ma lvcmos 3.3 8ma drive, slow slew rate 1.39 1.45 1.51 ns lvcmos33_12ma lvcmos 3.3 12ma drive, slow slew rate 1.21 1.27 1.33 ns lvcmos33_16ma lvcmos 3.3 16ma drive, slow slew rate 1.43 1.49 1.55 ns lvcmos33_20ma lvcmos 3.3 20ma drive, slow slew rate 1.23 1.28 1.34 ns lvcmos25_4ma lvcmos 2.5 4ma drive, slow slew rate 1.66 1.70 1.74 ns lvcmos25_8ma lvcmos 2.5 8ma drive, slow slew rate 1.39 1.43 1.46 ns lvcmos25_12ma lvcmos 2.5 12ma drive, slow slew rate 1.20 1.24 1.28 ns lvcmos25_16ma lvcmos 2.5 16ma drive, slow slew rate 1.42 1.45 1.49 ns lvcmos25_20ma lvcmos 2.5 20ma drive, slow slew rate 1.22 1.26 1.29 ns lvcmos18_4ma lvcmos 1.8 4ma drive, slow slew rate 1.61 1.65 1.68 ns lvcmos18_8ma lvcmos 1.8 8ma drive, slow slew rate 1.32 1.36 1.39 ns lvcmos18_12ma lvcmos 1.8 12ma drive, slow slew rate 1.14 1.17 1.21 ns lvcmos18_16ma lvcmos 1.8 16ma drive, slow slew rate 1.35 1.38 1.42 ns lvcmos15_4ma lvcmos 1.5 4ma drive, slow slew rate 1.57 1.60 1.64 ns lvcmos15_8ma lvcmos 1.5 8ma drive, slow slew rate 0.01 0.01 0.00 ns lvcmos12_2ma lvcmos 1.2 2ma drive, slow slew rate 1.51 1.54 1.58 ns lvcmos12_6ma lvcmos 1.2 6ma drive, slow slew rate -0.02 -0.02 -0.02 ns pci33 pci, vccio = 3.0v 0.19 0.21 0.24 ns 1. timing adders are characterized but not tested on every device. 2. lvcmos timing measured with the load sp ecified in switching test condition table. 3. all other standards tested accordi ng to the appropriate specifications. 4. not all i/o standards and drive strengths are supported for all banks. see the architecture section of this data sheet for de tails. 5. commercial timing numbers are shown. industrial numbers are typically slower and can be extracted from the isplever software. latticeecp3 family timing adders 1, 2, 3, 4, 5 (continued) over recommended commercial operating conditions buffer type description -8 -7 -6 units
3-31 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet latticeecp3 maximum i/o buffer speed 1, 2, 3, 4, 5, 6 over recommended operating conditions buffer description max. units maximum input frequency lv d s 2 5 lv d s, v ccio = 2.5v 400 mhz mlvds25 mlvds, emulated, v ccio = 2.5v 400 mhz blvds25 blvds, emulated, v ccio = 2.5v 400 mhz pplvds point-to-point lvds 400 mhz trlvds transition-reduced lvds 612 mhz mini lvds mini lvds 400 mhz lvpecl33 lvpecl, emulated, v ccio = 3.0v 400 mhz hstl18 (all supported classed) hstl_18 class i, ii, v ccio = 1.8v 400 mhz hstl15 hstl_15 class i, v ccio = 1.5v 400 mhz sstl33 (all supported classed) sstl_3 class i, ii, v ccio = 3.0v 400 mhz sstl25 (all supported classed) sstl_2 class i, ii, v ccio = 2.5v 400 mhz sstl18 (all supported classed) sstl_18 class i, ii, v ccio = 1.8v 400 mhz lvttl33 lvttl, v ccio = 3.0v 166 mhz lv c m o s 3 3 lv c m o s, v ccio = 3.0v 166 mhz lv c m o s 2 5 lv c m o s, v ccio = 2.5v 166 mhz lv c m o s 1 8 lv c m o s, v ccio = 1.8v 166 mhz lvcmos15 lvcmos 1.5, v ccio = 1.5v 166 mhz lvcmos12 lvcmos 1.2, v ccio = 1.2v 166 mhz pci33 pci, v ccio = 3.3v 66 mhz maximum output frequency lvds25e lvds, emulated, v ccio = 2.5v 300 mhz lv d s 2 5 lv d s, v ccio = 2.5v 612 mhz mlvds25 mlvds, emulated, v ccio = 2.5v 300 mhz rsds25 rsds, emulated, v ccio = 2.5v 612 mhz blvds25 blvds, emulated, v ccio = 2.5v 300 mhz pplvds point-to-point lvds 612 mhz lvpecl33 lvpecl, emulated, v ccio = 3.0v 612 mhz mini-lvds mini lvds 612 mhz hstl18 (all supported classed) hstl_18 class i, ii, v ccio = 1.8v 200 mhz hstl15 (all supported classed) hstl_15 class i, v ccio = 1.5v 200 mhz sstl33 (all supported classed) sstl_3 class i, ii, v ccio = 3.0v 233 mhz sstl25 (all supported classed) sstl_2 class i, ii, v ccio = 2.5v 233 mhz sstl18 (all supported classed) sstl_18 class i, ii, v ccio = 1.8v 266 mhz lvttl33 lvttl, v ccio = 3.0v 166 mhz lvcmos33 (for all drives) lvcmos, 3.3v 166 mhz lvcmos25 (for all drives) lvcmos, 2.5v 166 mhz lvcmos18 (for all drives) lvcmos, 1.8v 166 mhz lvcmos15 (for all drives) lvcmos, 1.5v 166 mhz lvcmos12 (for all drives except 2ma) lvcmos, v ccio = 1.2v 166 mhz lvcmos12 (2ma drive) lvcmos, v ccio = 1.2v 100 mhz
3-32 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet pci33 pci, v ccio = 3.3v 66 mhz 1. these maximum speeds are characterized but not tested on every device. 2. maximum i/o speed for differential output standards emulated with resistors depends on the layout. 3. lvcmos timing is measured with the load specified in the switching test conditions table of this document. 4. all speeds are measured at fast slew. 5. actual system operation may vary depending on user logic implementation. 6. maximum data rate equals 2 times the clock rate when utilizing ddr. latticeecp3 maximum i/o buffer speed (continued) 1, 2, 3, 4, 5, 6 over recommended operating conditions buffer description max. units
3-33 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet sysclock pll timing over recommended operating conditions parameter descriptions conditions clock min. typ. max. units f in input clock frequency (clki, clkfb) edge clock 2 ? 500 mhz primary clock 2 ? 420 mhz f out output clock frequency (clkop, clkos) edge clock 4 ? 500 mhz primary clock 4 ? 420 mhz f out1 k-divider output freq uency clkok 0.03125 ? 250 mhz f out2 k2-divider output frequency clkok2 0.667 ? 166 mhz f vco pll vco frequency 500 ? 1000 mhz f pfd 3 phase detector input frequency edge clock 2 ? 500 mhz primary clock 2 ? 420 mhz ac characteristics t pa programmable delay unit 65 130 260 ps t dt output clock duty cycle (clkos, at 50% setting) edge clock 45 50 55 % f out ?? 250 mhz primary clock 45 50 55 % f out > 250mhz primary clock 30 50 70 % t cpa coarse phase shift error (clkos, at all settings) -5 0 +5 % of period t opw output clock pulse width high or low (clkos) 1.8 ? ? ns t opjit 1 output clock period jitter f out ? 420mhz ? ? 200 p-p 420mhz > f out ? 100mhz ? ? 250 p-p f out < 100mhz ? ? 0.025 uipp t sk input clock to output clock skew when n/m = integer ??500p-p t lock 2 lock time 2 to 25 mhz ? ? 200 us 25 to 500 mhz ? ? 50 us t unlock reset to pll unlock time to ensure fast reset ? ? 50 ns t hi input clock high time 90% to 90% 0.5 ? ? ns t lo input clock low time 10% to 10% 0.5 ? ? ns t ipjit input clock period jitter ? ? 400 p-p t rst reset signal pulse width high, resetm, resetk 10 ? ? ns reset signal pulse width high, cntrst 500 ?? ns 1. jitter sample is taken over 10,000 samples of the primary p ll output with clean reference clock with no additional i/o toggl ing. 2. output clock is valid after t lock for pll reset and dynamic delay adjustment. 3. period jitter and cycle-to-cycle jitter numbers are guaranteed for f pfd > 4mhz. for f pfd < 4mhz, the jitter numbers may not be met in cer- tain conditions. please contact the factory for f pfd < 4mhz.
3-34 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet dll timing over recommended operating conditions parameter description condit ion min. typ. max. units f ref input reference clock frequency (on-chip or ? off-chip) 133 ? 500 mhz f fb feedback clock frequency (on-chip or off-chip) 133 ? 500 mhz f clkop 1 output clock frequency, clkop 133 ? 500 mhz f clkos 2 output clock frequency, clkos 33.3 ? 500 mhz t pjit output clock period jitter (clean input) ? 200 ps p-p t duty output clock duty cycle (at 50% levels, 50% duty cycle input clock, 50% duty cycle circuit turned off, time reference delay mode) edge clock 40 60 % primary clock 30 70 % t dutytrd output clock duty cycle (at 50% levels, arbitrary duty cycle input clock, 50% duty cycle circuit enabled, time reference delay mode) primary clock < 250mhz 45 55 % primary clock ?? 250mhz 30 70 % edge clock 45 55 % t dutycir output clock duty cycle (at 50% levels, arbitrary duty cycle input clock, 50% duty cycle circuit enabled, clock injection removal mode) with dll cascading primary clock < 250mhz 40 60 % primary clock ? 250mhz 30 70 % edge clock 45 55 % t skew 3 output clock to clock sk ew between two outputs with the same phase setting ??100ps t phase phase error measured at device pads between off-chip reference clock and feedback clocks ? ? +/-400 ps t pwh input clock minimum pulse width high (at 80% level) 550 ? ? ps t pwl input clock minimum pulse width low (at 20% level) 550 ? ? ps t instb input clock period jitter ? ? 500 p-p t lock dll lock time 8 ? 8200 cycles t rswd digital reset minimum pulse width (at 80% level) 3 ? ? ns t del delay step size 27 45 70 ps t range1 max. delay setting for single delay block ? (64 taps) 1.9 3.1 4.4 ns t range4 max. delay setting for four chained delay blocks 7.6 12.4 17.6 ns 1. clkop runs at the same frequency as the input clock. 2. clkos minimum frequency is obtained with divide by 4. 3. this is intended to be a ?path-matching? desi gn guideline and is not a m easurable specification.
3-35 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet serdes high-speed data transmitter 1 table 3-6. serial output timing and levels table 3-7. channel output jitter symbol description frequency min. typ. max. units v tx-diff-p-p-1.44 differential swing (1.44v setting) 1, 2 0.25 to 3.125 gbps 1150 1440 1730 mv, p-p v tx-diff-p-p-1.35 differential swing (1.35v setting) 1, 2 0.25 to 3.125 gbps 1080 1350 1620 mv, p-p v tx-diff-p-p-1.26 differential swing (1.26v setting) 1, 2 0.25 to 3.125 gbps 1000 1260 1510 mv, p-p v tx-diff-p-p-1.13 differential swing (1.13v setting) 1, 2 0.25 to 3.125 gbps 840 1130 1420 mv, p-p v tx-diff-p-p-1.04 differential swing (1.04v setting) 1, 2 0.25 to 3.125 gbps 780 1040 1300 mv, p-p v tx-diff-p-p-0.92 differential swing (0.92v setting) 1, 2 0.25 to 3.125 gbps 690 920 1150 mv, p-p v tx-diff-p-p-0.87 differential swing (0.87v setting) 1, 2 0.25 to 3.125 gbps 650 870 1090 mv, p-p v tx-diff-p-p-0.78 differential swing (0.78v setting) 1, 2 0.25 to 3.125 gbps 585 780 975 mv, p-p v tx-diff-p-p-0.64 differential swing (0.64v setting) 1, 2 0.25 to 3.125 gbps 480 640 800 mv, p-p v ocm output common mode voltage ? v ccob -0.75 v ccob -0.60 v ccob -0.45 v t tx-r rise time (20% to 80%) ? 145 185 265 ps t tx-f fall time (80% to 20%) ? 145 185 265 ps z tx-oi-se output impedance 50/75/hiz ohms ? (single ended) ?-20% 50/75/ hi z +20% ohms r lt x - r l return loss (with package) ? 10 db t tx-intraskew lane-to-lane tx skew within a ? serdes quad block (intra-quad) ? ? ? 200 ps t tx-interskew 3 lane-to-lane skew between serdes quad blocks (inter-quad) ? ? ? 1ui +200 ps 1. all measurements are with 50 ohm impedance. 2. see tn1176, latticeecp3 serdes/pcs usage guide for actual binary settings and the min-max range. 3. inter-quad skew is between all serdes channels on the device and requires the use of a low skew internal reference clock. description frequency min. typ. max. units deterministic 3.125 gbps ? ? 0.17 ui, p-p random 3.125 gbps ? ? 0.25 ui, p-p total 3.125 gbps ? ? 0.35 ui, p-p deterministic 2.5gbps ? ? 0.17 ui, p-p random 2.5gbps ? ? 0.20 ui, p-p total 2.5gbps ? ? 0.35 ui, p-p deterministic 1.25 gbps ? ? 0.10 ui, p-p random 1.25 gbps ? ? 0.22 ui, p-p total 1.25 gbps ? ? 0.24 ui, p-p deterministic 622 mbps ? ? 0.10 ui, p-p random 622 mbps ? ? 0.20 ui, p-p total 622 mbps ? ? 0.24 ui, p-p deterministic 250 mbps ? ? 0.10 ui, p-p random 250 mbps ? ? 0.18 ui, p-p total 250 mbps ? ? 0.24 ui, p-p note: values are measured with prbs 2 7 -1, all channels operating, fpga logic active, i/os around serdes pins quiet, reference clock @ 10x mode.
3-36 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet serdes/pcs block latency table 3-8 describes the latency of each functional block in the transmitter and receiver. latency is given in parallel clock cycles. figure 3-12 shows the location of each block. table 3-8. serdes/pcs latency breakdown figure 3-12. transmitter and receiver latency block diagram item description min. avg. max. fixed bypass units transmit data latency 1 t1 fpga bridge - gearing disabled with different clocks 1 3 5 ? 1 word clk fpga bridge - gearing disabled with same clocks ? ? ? 3 1 word clk fpga bridge - gearing enabled 1 3 5 ? ? word clk t2 8b10b encoder ? ? ? 2 1 word clk t3 serdes bridge transmit ? ? ? 2 1 word clk t4 serializer: 8-bit mode ? ? ? 15 + ? 1? ui + ps serializer: 10-bit mode ? ? ? 18 + ? 1? ui + ps t5 pre-emphasis on ? ? ? 1 + ? 2?ui + ps pre-emphasis off ? ? ? 0 + ? 3?ui + ps receive data latency 2 r1 equalization on ? ? ? ? 1?ui + ps equalization off ? ? ? ? 2?ui + ps r2 deserializer: 8-bit mode ? ? ? 10 + ? 3? ui + ps deserializer: 10-bit mode ? ? ? 12 + ? 3? ui + ps r3 serdes bridge receive ? ? ? 2 ? word clk r4 word alignment 3.1 ? 4 ? ? word clk r5 8b10b decoder ? ? ? 1 ? word clk r6 clock tolerance compensation 7 15 23 1 1 word clk r7 fpga bridge - gearing disabled with different clocks 1 3 5 ? 1 word clk fpga bridge - gearing disabled with same clocks ? ? ? 3 1 word clk fpga bridge - gearing enabled 1 3 5 ? ? word clk 1. ? 1 = -245ps, ? 2 = +88ps, ? 3 = +112ps. 2. ? 1 = +118ps, ? 2 = +132ps, ? 3 = +700ps. hdoutpi hdoutni deserializer 1:8/1:10 polarity adjust elastic buffer fifo encoder serdes pcs bypass transmitter receiver recovered clock fpga receive clock fpga receive data transmit data cdr refclk hdinpi hdinni eq polarity adjust up sample fifo serdes bridge fpga bridge serializer 8:1/10:1 wa dec fpga ebrd clock transmit clock tx pll refclk fpga core down sample fifo bypass bypass bypass bypass bypass bypass r1 r2 r3 r4 r5 r6 t1 t2 t3 t4 transmit clock
3-37 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet serdes high speed data receiver table 3-9. serial input data specifications input data jitter tolerance a receiver?s ability to tolerate incoming signal jitter is very dependent on jitte r type. high speed serial interface stan- dards have recognized the dependency on jitter type and have specifications to indicate tolerance levels for differ- ent jitter types as they relate to specific protocols. sinu soidal jitter is considered to be a worst case jitter type. table 3-10. receiver total jitter tolerance specification symbol description min. typ. max. units rx-cid s stream of nontransitions 1 ? (cid = consecutive identical digits) @ 10 -12 ber 3.125g ? ? 136 bits 2.5g ? ? 144 1.485g ? ? 160 622m ? ? 204 270m ? ? 228 155m ? ? 296 v rx-diff-s differential input sensitivity 150 ? 1760 mv, p-p v rx-in input levels 0 ? v cca +0.5 4 v v rx-cm-dc input common mode range (dc coupled) 0.6 ? v cca v v rx-cm-ac input common mode range (ac coupled) 3 0.1 ? v cca +0.2 v t rx-relock scdr re-lock time 2 ?1000?bits z rx-term input termination 50/75 ohm/high z -20% 50/75/hiz +20% ohms rl rx-rl return loss (without package) 10 ? ? db 1. this is the number of bits allowed without a tr ansition on the incoming data st ream when using dc coupling. 2. this is the typical number of bit times to re-lock to a new phase or frequency within +/- 300 ppm, assuming 8b10b encoded dat a. 3. ac coupling is used to interface to lvpecl and lvds. lvds in terfaces are found in laser drivers and fibre channel equipment. lv d s i n t e r - faces are generally found in 622 mbps serdes devices. 4. up to 1.76v. description frequency condition min. typ. max. units deterministic 3.125 gbps 600 mv differential eye ? ? 0.47 ui, p-p random 600 mv differential eye ? ? 0.18 ui, p-p total 600 mv differential eye ? ? 0.65 ui, p-p deterministic 2.5 gbps 600 mv differential eye ? ? 0.47 ui, p-p random 600 mv differential eye ? ? 0.18 ui, p-p total 600 mv differential eye ? ? 0.65 ui, p-p deterministic 1.25 gbps 600 mv differential eye ? ? 0.47 ui, p-p random 600 mv differential eye ? ? 0.18 ui, p-p total 600 mv differential eye ? ? 0.65 ui, p-p deterministic 622 mbps 600 mv differential eye ? ? 0.47 ui, p-p random 600 mv differential eye ? ? 0.18 ui, p-p total 600 mv differential eye ? ? 0.65 ui, p-p note: values are measured with cjpat, all channels operating, fpga logic active, i/os around serde s pins quiet, voltages are no minal, room temperature.
3-38 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet table 3-11. periodic receiver jitter tolerance specification description frequency condition min. typ. max. units periodic 2.97 gbps 600 mv differential eye ? ? 0.24 ui, p-p periodic 2.5 gbps 600 mv differential eye ? ? 0.22 ui, p-p periodic 1.485 gbps 600 mv differential eye ? ? 0.24 ui, p-p periodic 622 mbps 600 mv differential eye ? ? 0.15 ui, p-p periodic 155 mbps 600 mv differential eye ? ? 0.5 ui, p-p note: values are measured with prbs 2 7 -1, all channels operating, fpga logic active, i/os around serdes pins quiet, voltages are nominal, room temperature.
3-39 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet serdes external reference clock the external reference clock selection and its interface are a critical part of system applications for this product. table 3-12 specifies reference clock requirements, over the full range of operating conditions. figure 3-13. serdes external reference clock waveforms table 3-12. external reference clock specification (refclkp/refclkn) symbol description min. typ. max. units f ref frequency range 15 ? 320 mhz f ref-ppm frequency tolerance 4 -1000 ? 1000 ppm v ref-in-se input swing, single-ended clock 1 200 ? v cca mv, p-p v ref-in-diff input swing, differential clock 200 ? 2*v cca mv, p-p differential v ref-in input levels 0 ? v cca + 0.3 v v ref-cm-ac input common mode range (ac coupled) 2 0.125 ? v cca v d ref duty cycle 3 40 ? 60 % t ref-r rise time (20% to 80%) 200 500 1000 ps t ref-f fall time (80% to 20%) 200 500 1000 ps z ref-in-term-diff differential input termination -20% 100/2k +20% ohms c ref-in-cap input capacitance ? ? 7 pf 1. the signal swing for a single-ended input clock must be as large as the p-p diff erential swing of a differential input clock to get the same gain at the input receiver. lower swings for the cloc k may be possible, but will tend to increase jitter. 2. when ac coupled, the input common mode range is determined by: ? (min input level) + (peak-to-peak input swing)/2 ? (input common mode voltage) ? (max input level) - (p eak-to-peak input swing)/2 3. measured at 50% amplitude. 4. depending on the application, the pll_lol_set and cdr_lol_set cont rol registers may be adjusted for other tolerance values as described in tn1176, latticeecp3 serdes/pcs usage guide .
3-40 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet pci express electrical an d timing characteristics ac and dc characteristics over recommended operating conditions symbol description test conditions min typ max units transmit 1 ui unit interval 399.88 400 400.12 ps v tx-diff_p-p differential peak-to-peak output voltage 0.8 1.0 1.2 v v tx-de-ratio de-emphasis differential output voltage ratio -3 -3.5 -4 db v tx-cm-ac_p rms ac peak common-mode output voltage ?? 20 mv v tx-rcv-detect amount of voltage change allowed dur- ing receiver detection ?? 600 mv v tx-dc-cm tx dc common mode voltage 0 ? v ccob + 5% v i tx-short output short circuit current v tx-d+ =0.0v v tx-d- =0.0v ?? 90 ma z tx-diff-dc differential output impedance 80 100 120 ohms rl tx-diff differential return loss 10 ? ? db rl tx-cm common mode return loss 6.0 ? ? db t tx-rise tx output rise time 20 to 80% 0.125 ? ? ui t tx-fall tx output fall time 20 to 80% 0.125 ? ? ui l tx-skew lane-to-lane static output skew for all lanes in port/link ?? 1.3 ns t tx-eye transmitter eye width 0.75 ? ? ui t tx-eye-median-to-max-jitter maximum time between jitter median and maximum deviation from median ? ? 0.125 ui receive 1, 2 ui unit interval 399.88 400 400.12 ps v rx-diff_p-p differential peak-to-peak input voltage 0.34 3 ?1.2v v rx-idle-det-diff_p-p idle detect threshold voltage 65 ? 340 3 mv v rx-cm-ac_p receiver common mode voltage for ac coupling ?? 150 mv z rx-diff-dc dc differential input impedance 80 100 120 ohms z rx-dc dc input impedance 40 50 60 ohms z rx-high-imp-dc power-down dc input impedance 200k ? ? ohms rl rx-diff differential return loss 10 ? ? db rl rx-cm common mode return loss 6.0 ? ? db t rx-idle-det-diff-entertime maximum time required for receiver to recognize and signal an unexpected idle on link ?? ? ms 1. values are measured at 2.5 gbps. 2. measured with external ac-coupling on the receiver. 3.not in compliance with pci express 1.1 standard.
3-41 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet xaui/serial rapid i/o type 3 electr ical and timing characteristics ac and dc characteristics table 3-13. transmit over recommended operating conditions table 3-14. receive and jitter tolerance over recommended operating conditions symbol description test conditions min. typ. max. units t rf differential rise/fall time 20%-80% ? 80 ? ps z tx_diff_dc differential impedance 80 100 120 ohms j tx_ddj 2, 3, 4 output data deterministic jitter ? ? 0.17 ui j tx_tj 1, 2, 3, 4 total output data jitter ? ? 0.35 ui 1. total jitter includes both deterministic jitter and random jitter. 2. jitter values are measured with each cml output ac c oupled into a 50-ohm impedance (100-ohm differential impedance). 3. jitter and skew are specified between differential cr ossings of the 50% threshold of the reference signal. 4. values are measured at 2.5 gbps. symbol description test cond itions min. typ. max. units rl rx_diff differential return loss from 100 mhz to 3.125 ghz 10 ? ? db rl rx_cm common mode return loss from 100 mhz to 3.125 ghz 6??db z rx_diff differential termination resistance 80 100 120 ohms j rx_dj 1, 2, 3 deterministic jitter tolerance (peak-to-peak) ? ? 0.37 ui j rx_rj 1, 2, 3 random jitter tolerance (peak-to-peak) ? ? 0.18 ui j rx_sj 1, 2, 3 sinusoidal jitter tolerance (peak-to-peak) ? ? 0.10 ui j rx_tj 1, 2, 3 total jitter tolerance (peak-to-peak) ? ? 0.65 ui t rx_eye receiver eye opening 0.35 ? ? ui 1. total jitter includes deterministic jitte r, random jitter and sinusoidal jitter. the sinusoidal jitter tolerance mask is sho wn in figure 3-14. 2. jitter values are measured with each hi gh-speed input ac coupled into a 50-ohm impedance. 3. jitter and skew are specified between differential cr ossings of the 50% threshold of the reference signal. 4. jitter tolerance parameters are characte rized when full rx e qualization is enabled. 5. values are measured at 2.5 gbps.
3-42 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet figure 3-14. xaui sinusoidal jitter tolerance mask note: the sinusoidal jitter tolerance is measured with at least 0.37uipp of deterministic jitter (dj) and the sum of dj and rj (random jitter) is at least 0.55uipp. therefore, the sum of dj, rj and sj (sinusoidal jitter) is at least 0.65uipp (dj = 0.37, rj = 0.18, sj = 0.1). data_rate/ 1667 20mhz 20db/dec 8.5ui sj amplitude sj frequency 0.1ui
3-43 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet serial rapid i/o type 2 electr ical and timing characteristics ac and dc characteristics table 3-15. transmit table 3-16. receive and jitter tolerance symbol description test conditions min. typ. max. units t rf 1 differential rise/fall time 20%-80% ? 80 ? ps z tx_diff_dc differential impedance 80 100 120 ohms j tx_ddj 3, 4, 5 output data determin istic jitter ? ? 0.17 ui j tx_tj 2, 3, 4, 5 total output data jitter ? ? 0.35 ui 1. rise and fall times meas ured with board trace, connecto r and approximately 2.5pf load. 2. total jitter includes both deterministic jitter and random jitter. the random jitter is the total jitter minus the actual de terministic jitter. 3. jitter values are measured with each cml output ac c oupled into a 50-ohm impedance (100-ohm differential impedance). 4. jitter and skew are specified between differential cr ossings of the 50% threshold of the reference signal. 5. values are measured at 2.5 gbps. symbol description test conditions min. typ. max. units rl rx_diff differential return loss from 100 mhz to 2.5 ghz 10 ? ? db rl rx_cm common mode return loss from 100 mhz to 2.5 ghz 6 ? ? db z rx_diff differential termination resistance 80 100 120 ohms j rx_dj 2, 3, 4, 5 deterministic jitter tolerance (peak-to-peak) ? ? 0.37 ui j rx_rj 2, 3, 4, 5 random jitter tolerance (peak-to-peak) ? ? 0.18 ui j rx_sj 2, 3, 4, 5 sinusoidal jitter tolerance (peak-to-peak) ? ? 0.10 ui j rx_tj 1, 2, 3, 4, 5 total jitter tolerance (peak-to-peak) ? ? 0.65 ui t rx_eye receiver eye opening 0.35 ? ? ui 1. total jitter includes deterministic jitte r, random jitter and sinusoidal jitter. the sinusoidal jitter tolerance mask is sho wn in figure 3-14. 2. jitter values are measured with each hi gh-speed input ac coupled into a 50-ohm impedance. 3. jitter and skew are specified between differential cro ssings of the 50% threshold of the reference signal. 4. jitter tolerance, differential input sensitivity and receiv er eye opening parameters are char acterized when full rx equaliza tion is enabled. 5. values are measured at 2.5 gbps.
3-44 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet gigabit ethernet/serial rapid i/o ty pe 1/sgmii electrical and timing ? characteristics ac and dc characteristics table 3-17. transmit table 3-18. receive and jitter tolerance symbol description test conditions min. typ. max. units t rf differential rise/fall time 20%-80% ? 80 ? ps z tx_diff_dc differential impedance 80 100 120 ohms j tx_ddj 3, 4, 5 output data deterministic jitter ? ? 0.10 ui j tx_tj 2, 3, 4, 5 total output data jitter ? ? 0.24 ui 1. rise and fall times measured with board trace, connector and approximately 2.5pf load. 2. total jitter includes both deterministic jitter and random jitter. the random jitter is the total jitter minus the actual de terministic jitter. 3. jitter values are measured with each cml output ac c oupled into a 50-ohm impedance (100-ohm differential impedance). 4. jitter and skew are specified between differential cr ossings of the 50% threshold of the reference signal. 5. values are measured at 1.25 gbps. symbol description test conditions min. typ. max. units rl rx_diff differential return loss from 100 mhz to 1.25 ghz 10 ? ? db rl rx_cm common mode return loss from 100 mhz to 1.25 ghz 6 ? ? db z rx_diff differential termination resistance 80 100 120 ohms j rx_dj 1, 2, 3, 4, 5 deterministic jitter tolerance (peak-to-peak) ? ? 0.34 ui j rx_rj 1, 2, 3, 4, 5 random jitter tolerance (peak-to-peak) ? ? 0.26 ui j rx_sj 1, 2, 3, 4, 5 sinusoidal jitter tolerance (peak-to-peak) ? ? 0.11 ui j rx_tj 1, 2, 3, 4, 5 total jitter tolerance (peak-to-peak) ? ? 0.71 ui t rx_eye receiver eye opening 0.29 ? ? ui 1. total jitter includes deterministic jitte r, random jitter and sinusoidal jitter. the sinusoidal jitter tolerance mask is sho wn in figure 3-14. 2. jitter values are measured with each hi gh-speed input ac coupled into a 50-ohm impedance. 3. jitter and skew are specified between differential cr ossings of the 50% threshold of the reference signal. 4. jitter tolerance, differential input sensitivity and receiver eye opening parameters are charac terized when full rx equaliza tion is enabled. 5. values are measured at 1.25 gbps.
3-45 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet smpte sd/hd-sdi/3g-sdi (serial digita l interface) elect rical and timing characteristics ac and dc characteristics table 3-19. transmit table 3-20. receive table 3-21. reference clock symbol description test conditions min. typ. max. units br sdo serial data rate 270 ? 2975 mbps t jalignment 2 serial output jitter, alignment 270 mbps ? ? 0.20 ui t jalignment 2 serial output jitter, alignment 1485 mbps ? ? 0.20 ui t jalignment 1, 2 serial output jitter, alignment 2970mbps ? ? 0.30 ui t jtiming serial output jitter, timing 270 mbps ? ? 0.20 ui t jtiming serial output jitter, timing 1485 mbps ? ? 1.0 ui t jtiming serial output jitter, timing 2970 mbps ? ? 2.0 ui notes: 1. timing jitter is measured in accordance with smpte rp 1 84-1996, smpte rp 192-1996 and the applicable serial data transmissio n stan- dard, smpte 259m-1997 or smpte 292m (proposed). a co lor bar test pattern is used.the value of f sclk is 270 mhz or 360 mhz for smpte 259m, 540 mhz for smpte 344m or 1485 mhz for smpte 292m serial data rates. see the timing jitter bandpass section. 2. jitter is defined in accordance with smpte rp1 184-1996 as: ji tter at an equipment output in the absence of input jitter. 3. all tx jitter is measured at the output of an industry standard cable driver; connection to the cable driver is via a 50 ohm impedance differen- tial signal from the lattice serdes device. 4. the cable driver drives: rl=75 ohm, ac-coupled at 270, 1485, or 2970 mbps, rreflvl=rrefpre=4.75kohm 1%. symbol description test conditions min. typ. max. units br sdi serial input data rate 270 ? 2970 mbps cid stream of non-transitions (=consecutive identical digits) 7(3g)/26(smpte triple rates) @ 10-12 ber ??bits symbol description test cond itions min. typ. max. units f vclk video output clock frequency 27 ? 74.25 mhz dc v duty cycle, video clock 45 50 55 %
3-46 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet hdmi (high-definition multimedia interface) electrical and timing ? characteristics ac and dc characteristics table 3-22. transmit and receive 1, 2 symbol description spec. compliance units min. spec. max. spec. transmit intra-pair skew ?75ps inter-pair skew ? 800 ps tmds differential clock jitter ? 0.25 ui receive r t termination resistance 40 60 ohms v icm input ac common mode voltage (50-ohm setting) ? 50 mv tmds clock jitter clock jitter tolerance ? 0.25 ui 1. output buffers must drive a translation device. max. speed is 2gbps. if translation device does not modify rise/fall time, th e maximum speed is 1.5gbps. 2. input buffers must be ac coupled in order to support the 3.3v common mode. generally, hdmi inputs are terminated by an extern al cable equalizer before data/clock is forwar ded to the latticeecp3 device.
3-47 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet figure 3-15. test loads jitter bandpass jitter frequency 0db v ddio s 1 s 2 c l i oh i ol cmos outputs test loads timing jitter bandpass hi-z test eqpt. 5 k (atteunation 0db) c l including probe and jig capacitance, 3pf max. s 1 - open, s 2 - closed for v oh measurement. s 1 - closed, s 2 - open for v ol measurement. 10hz passband ripple < 1db stopband rejection <20db slopes: 20db/decade >1/10 f sclk v ddsd c l sdo sdo 1.0f 75 test eqpt. (atteunation 0db) 75 1% v ddsd c l sdo sdo 1.0f *risetime compensation. 24.9 1% 5.5-30pf* 50 test eqpt. (atteunation 3.5db) 75 1%
3-48 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet latticeecp3 sysconfig port timing specifications over recommended operating conditions parameter description min. max. units por, configuration init ialization, and wakeup t icfg time from the application of v cc , v ccaux or v ccio8 * (whichever is the last to cross the por trip point) to the rising edge of initn master mode ? 23 ms slave mode ? 6 ms t vmc time from t icfg to the valid master mclk ? 5 s t prgm programn low time to start configuration 25 ? ns t prgmrj programn pin puls e rejection ? 10 ns t dppinit delay time from programn low to initn low ? 37 ns t dppdone delay time from programn low to done low ? 37 ns t dinit programn high to initn high delay ? 1 ms t mwc additional wake master clock signals after done pin is high 100 500 cycles t cz mclk from active to low to high-z ? 300 ns all configuration modes t sucdi data setup time to cclk/mclk 5 ? ns t hcdi data hold time to cclk/mclk 1 ? ns t codo cclk/mclk to dout in flowthrough mode ? 12 ns slave serial t ssch cclk minimum high pulse 5 ? ns t sscl cclk minimum low pulse 5 ? ns f cclk cclk frequency without encryption ? 33 mhz with encryption ? 20 mhz master and slave parallel t sucs csn[1:0] setup time to cclk/mclk 7 ? ns t hcs csn[1:0] hold time to cclk/mclk 1 ? ns t suwd writen setup time to cclk/mclk 7 ? ns t hwd writen hold time to cclk/mclk 1 ? ns t dcb cclk/mclk to busy delay time ? 12 ns t cord cclk to out for read data ? 12 ns t bsch cclk minimum high pulse 6 ? ns t bscl cclk minimum low pulse 6 ? ns t bscyc byte slave cycle time 30 ? ns f cclk cclk/mclk frequency without encryption ? 33 mhz with encryption ? 20 mhz master and slave spi t cfgx initn high to mclk low ? 80 ns t csspi initn high to csspin low 0.2 2 s t socdo mclk low to output valid ? 15 ns t cspid csspin[0:1] low to first mclk edge setup time 0.3 s f cclk cclk frequency without encryption ? 33 mhz with encryption ? 20 mhz t ssch cclk minimum high pulse 5 ? ns t sscl cclk minimum low pulse 5 ? ns t hlch holdn low setup time (relative to cclk) 5 ? ns
3-49 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet figure 3-16. sysconfig parallel port read cycle t chhh holdn low hold time (relative to cclk) 5 ? ns master and slave spi (continued) t chhl holdn high hold time (relative to cclk) 5 ? ns t hhch holdn high setup time (relative to cclk) 5 ? ns t hlqz holdn to output high-z ? 9 ns t hhqx holdn to output low-z ? 9 ns parameter min. max. units master clock frequency selected value - 15% selected value + 15% mhz duty cycle 40 60 % latticeecp3 sysconfig port timing specifications (continued) over recommended operating conditions parameter description min. max. units cclk cs1n csn writen busy d[0:7] t sucs t hcs t suwd t cord t dcb t hwd t bscyc t bsch t bscl byte 0 byte 1 byte 2 byte n* *n = last byte of read cycle.
3-50 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet figure 3-17. sysconfig parallel port write cycle figure 3-18. sysconfig master serial port timing figure 3-19. sysconfig slave serial port timing cclk 1 cs1n csn writen busy d[0:7] t sucs t hcs t suwd t hcbdi t dcb t hwd t bscyc t bsch t bscl t sucbdi byte 0 byte 1 byte 2 byte n 1. in master parallel mode the fpga provides cclk (mclk). in slave parallel mode the external device provides cclk. cclk (output) din dout t sumcdi t hmcdi t codo cclk (input) din dout t suscdi t hscdi t codo t sscl t ssch
3-51 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet figure 3-20. power-on-reset (por) timing figure 3-21. sysconfig port timing cclk 2 done v cc / v ccaux / v ccio8 1 cfg[2:0] 3 t icfg valid initn t vmc 1. time taken from v cc , v ccaux or v ccio8 , whichever is the last to cross the por trip point. 2. device is in a master mode (spi, spim). 3. the cfg pins are normally static (hard wired).
3-52 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet figure 3-22. configuration from programn timing figure 3-23. wake-up timing done cclk cfg[2:0] 1 user i/o initn programn t prgmrj t dinit t dppinit t dinitd t iodiss valid 1. the cfg pins are normally static (hard wired) cclk done programn user i/o initn t ioenss wake-up t mwc
3-53 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet figure 3-24. master spi configuration waveforms opcode address 0 1 2 3 ? 7 8 9 10 ? 31 32 33 34 ? 127 128 vcc programn done initn csspin cclk sispi sospi capture cfgx capture cr0 ignore valid bitstream
3-54 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet jtag port timing specifications over recommended operating conditions figure 3-25. jtag port timing waveforms symbol parameter min max units f max tck clock frequency ? 25 mhz t btcp tck [bscan] clock pulse width 40 ? ns t btcph tck [bscan] clock pulse width high 20 ? ns t btcpl tck [bscan] clock pulse width low 20 ? ns t bts tck [bscan] setup time 10 ? ns t bth tck [bscan] hold time 8 ? ns t btrf tck [bscan] rise/fall time 50 ? mv/ns t btco tap controller falling edge of clock to valid output ? 10 ns t btcodis tap controller falling edge of clock to valid disable ? 10 ns t btcoen tap controller falling edge of clock to valid enable ? 10 ns t btcrs bscan test capture register setup time 8 ? ns t btcrh bscan test capture register hold time 25 ? ns t butco bscan test update register, falling edge of clock to valid output ? 25 ns t btuodis bscan test update register, falling edge of clock to valid disable ? 25 ns t btupoen bscan test update register, falling edge of clock to valid enable ? 25 ns tms tdi tck tdo data to be captured from i/o data to be driven out to i/o a t a d d i l a v a t a d d i l a v a t a d d i l a v a t a d d i l a v data captured t btcph t btcpl t btcoen t btcrs t btupoen t butco t btuodis t btcrh t btco t btcodis t bts t bth t btcp
3-55 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet switching test conditions figure 3-26 shows the output test load that is used for ac testing. the specific values for resistance, capacitance, voltage, and other test conditions are shown in table 3-23. figure 3-26. output test load, lvttl and lvcmos standards table 3-23. test fixture required components, non-terminated interfaces test condition r 1 r 2 c l timing ref. v t lvttl and other lvcmos settings (l -> h, h -> l) ?? 0pf lvcmos 3.3 = 1.5v ? lvcmos 2.5 = v ccio /2 ? lvcmos 1.8 = v ccio /2 ? lvcmos 1.5 = v ccio /2 ? lvcmos 1.2 = v ccio /2 ? lvcmos 2.5 i/o (z -> h) ? 1m ? 0pf v ccio /2 ? lvcmos 2.5 i/o (z -> l) 1m ? ? 0pf v ccio /2 v ccio lvcmos 2.5 i/o (h -> z) ? 100 0pf v oh - 0.10 ? lvcmos 2.5 i/o (l -> z) 100 ? 0pf v ol + 0.10 v ccio note: output test conditions for all other inte rfaces are determined by the respective standards. dut v t r1 r2 cl* test poi nt *cl includes test fixture and probe capacitance
3-56 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet sysi/o differential electrical characteristics transition reduced lvds (t rlvds dc specification) over recommended operating conditions mini lvds over recommended operating conditions symbol description min. nom. max. units v cco driver supply voltage (+/- 5%) 3.14 3.3 3.47 v v id input differential voltage 150 1200 mv v icm input common mode voltage 3 3.265 v v cco termination supply voltage 3.14 3.3 3.47 v r t termination resistance (off-chip) 45 50 55 ohms note: latticeecp3 only supports the trlvds receiver. parameter symbol description min. typ. max. units z o single-ended pcb trace impedance 30 50 75 ohms r t differential termination resistance 50 100 150 ohms v od output voltage, differential, |v op - v om |300?600mv v os output voltage, common mode, |v op + v om |/2 1 1.2 1.4 v ? v od change in v od , between h and l ? ? 50 mv ? v id change in v os , between h and l ? ? 50 mv v thd input voltage, differential, |v inp - v inm |200?600mv v cm input voltage, common mode, |v inp + v inm |/2 0.3+(v thd /2) ? 2.1-(v thd /2) t r , t f output rise and fall times, 20% to 80% ? ? 550 ps t oduty output clock duty cycle 40 ? 60 % note: data is for 6ma differential current drive. ot her differential driver curr ent options are available. current source vcco = 3.3v z 0 r t r t transmitter receiver
3-57 dc and switching characteristics lattice semiconductor latticee cp3 family data sheet point-to-point lvds (pplvds) over recommended operating conditions rsds over recommended operating conditions description min. typ. max. units output driver supply (+/- 5%) 3.14 3.3 3.47 v 2.25 2.5 2.75 v input differential voltage 100 400 mv input common mode voltage 0.2 2.3 v output differential voltage 130 400 mv output common mode voltage 0.5 0.8 1.4 v parameter symbol description min. typ. max. units v od output voltage, differential, r t = 100 ohms 100 200 600 mv v os output voltage, common mode 0.5 1.2 1.5 v i rsds differential driver output current 1 2 6 ma v thd input voltage differential 100 ? ? mv v cm input common mode voltage 0.3 ? 1.5 v t r , t f output rise and fall times, 20% to 80% ? 500 ? ps t oduty output clock duty cycle 35 50 65 % note: data is for 2ma drive. other differen tial driver current options are available.
www.latticesemi.com 4-1 ds1021 pinout information_01.2 march 2010 preliminary data sheet ds1021 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. signal descriptions signal name i/o description general purpose p[edge] [row/column number]_[a/b] i/o [edge] indicates the edge of the device on which the pad is located. valid edge designations are l (left), b (bottom), r (right), t (top). [row/column number] indicates the pfu row or the column of the device on which the pic exists. when edge is t (top) or b (bottom), only need to spec- ify column number. when edge is l (left) or r (right), only need to specify row number. [a/b] indicates the pio within the pic to which the pad is connected. some of these user-programmable pins are shared with special function pins. these pins, when not used as special purpose pins, can be programmed as i/os for user logic. during configuration the user-programmable i/os are tri-stated with an internal pull-up resistor enabl ed. if any pin is not used (or not bonded to a package pin), it is also tri-stat ed with an internal pull-up resistor enabled after configuration. p[edge][row number]e_[a/b/c/d] i these general purpose signals are input -only pins and are located near the plls. gsrn i global reset signal (activ e low). any i/o pin can be gsrn. nc ? no connect. reserved ? this pin is reserved and should not be connected to an ything on the board. gnd ? ground. dedicated pins. v cc ? power supply pins for core logic. dedicated pins. v ccaux ? auxiliary power supply pin. this dedicated pin powers all the differential and referenced input buffers. v cciox ? dedicated power supply pins for i/o bank x. v cca ? serdes, transmit, receive, pll and reference clock buffer power supply. v ccpll_[loc] ? general purpose pll supply pins where loc=l (left) or r (right). v ref1_x , v ref2_x ? reference supply pins for i/o bank x. pre-determined pins in each bank are assigned as v ref inputs. when not used, they may be used as i/o pins. vttx ? power supply for on-chip termination of i/os (required for ddr3 and lvds at 1.25gbps). xres 1 ? 10k ohm +/-1% resistor must be connected between this pad and ground. pll, dll and clock functions [loc][num]_gpll[t, c]_in_[index] i general purpose pll (gpll) input pads : lum, llm, rum, rlm, num = row from center, t = true and c = complement, index a,b,c...at each side. [loc][num]_gpll[t, c]_fb_[index] i optional feedback gpll input pads: lum, llm, rum, rlm, num = row from center, t = true and c = complement, index a,b,c...at each side. [loc]0_gdllt_in_[index] i/o general purpose dll (gdll) input pads where loc=rum or lum, t is true complement, index is a or b. [loc]0_gdllt_fb_[index] i/o optional feedback gdll input pads where loc=rum or lum, t is true complement, index is a or b. pclk[t, c][n:0]_[3:0] i primary clock pads, t = true and c = complement, n per side, indexed by bank and 0, 1, 2, 3 within bank. latticeecp3 family data sheet pinout information
4-2 pinout information lattice semiconductor latticee cp3 family data sheet [loc]dqs[num] i/o dq input/output pads: t (top), r (right), b (bottom), l (left), dqs, num = ball function number. [loc]dq[num] i/o dq input/output pads: t (top), r (right), b (bottom), l (left), dq, associated dqs number. test and programmin g (dedicated pins) tms i test mode select input, used to control the 1149.1 state machine. pull-up is enabled during configuration. tck i test clock input pin, used to clock the 1149.1 state machine. no pull-up enabled. tdi i test data in pin. used to load data into device using 1149.1 state machine. after power-up, this tap port can be activated for configuration by sending appropriate command. (note: once a co nfiguration port is selected it is locked. another configuration port cannot be selected until the power-up sequence). pull-up is enabled during configuration. tdo o output pin. test data out pin used to shift data out of a device using 1149.1. vccj ? power supply pin for jtag test access port. configuration pads (used during sysconfig) cfg[2:0] i mode pins used to specify configuratio n mode values latched on rising edge of initn. during configuration, a pu ll-up is enabled. these are dedicated pins. initn i/o open drain pin. indicates the fpga is re ady to be configured. during config- uration, a pull-up is enabled. it is a dedicated pin. programn i initiates configuration sequence when asserted low. this pin always has an active pull-up. it is a dedicated pin. done i/o open drain pin. indicates that the c onfiguration sequence is complete, and the startup sequence is in progress. it is a dedicated pin. cclk i input configuration clock for configuring an fpga in slave spi, serial, and cpu modes. it is a dedicated pin. mclk i/o output configuration clock for confi guring an fpga in spi, spim, and mas- ter configuration modes. busy/sispi o parallel configuration mode busy indicator. spi/spim mode data output. csn/sn/oen i/o parallel configuration mode active-low chip select. slave spi chip select. ? parallel burst flash output enable. cs1n/holdn/rdy i parallel configuration mode ac tive-low chip select. slave spi hold input. writen i write enable for parallel configuration modes. dout/cson/csspi1n o serial data output. chip select output. spi/spi m mode chip select. d[0]/spifastn i/o sysconfig port data i/o for parallel mode. open drain dur ing configuration. sysconfig port data i/o for spi or spim. when using the spi or spim mode, this pin should either be tied high or low, must not be left floating. open drain during configuration. d1 i/o parallel configuration i/o. open drain during configuration. d2 i/o parallel configuration i/o. open drain during configuration. d3/si i/o parallel configuration i/o. slave spi da ta input. open drain during configura- tion. d4/so i/o parallel configuration i/o. slave spi data output. open drain during configura- tion. d5 i/o parallel configuration i/o. open drain during configuration. d6/spid1 i/o parallel configuration i/o. spi/spim dat a input. open drain during configura- tion. signal descriptions (cont.) signal name i/o description
4-3 pinout information lattice semiconductor latticee cp3 family data sheet d7/spid0 i/o parallel configuration i/o. spi/spim dat a input. open drain during configura- tion. di/csspi0n/cen i/o serial data input for slav e serial mode. spi/spi m mode chip select. dedicated serdes signals 2 pcs[index]_hdinnm i high-speed input, negative channel m pcs[index]_hdoutnm o high-speed output, negative channel m pcs[index]_refclkn i negative reference clock input pcs[index]_hdinpm i high-speed input, positive channel m pcs[index]_hdoutpm o high-speed output, positive channel m pcs[index]_refclkp i positive reference clock input pcs[index]_vccobm ? output buffer power supply, channel m (1.2v/1.5) pcs[index]_vccibm ? input buffer power supply, channel m (1.2v/1.5v) 1. when placing switching i/os around these cr itical pins that are designed to supply t he device with the proper reference or su pply voltage, care must be given. 2. m defines the associated channel in the quad. signal descriptions (cont.) signal name i/o description
4-4 pinout information lattice semiconductor latticee cp3 family data sheet pics and ddr data (dq) pins associ ated with the ddr strobe (dqs) pin pics associated with dqs strobe pio within pic ddr strobe (dqs) and data (dq) pins for left and right edges of the device p[edge] [n-3] adq bdq p[edge] [n-2] adq bdq p[edge] [n-1] adq bdq p[edge] [n] a[edge]dqsn bdq p[edge] [n+1] adq bdq p[edge] [n+2] adq bdq for top edge of the device p[edge] [n-3] adq bdq p[edge] [n-2] adq bdq p[edge] [n-1] adq bdq p[edge] [n] a [edge]dqsn bdq p[edge] [n+1] adq bdq p[edge] [n+2] adq bdq note: ?n? is a row pic number.
4-5 pinout information lattice semiconductor latticee cp3 family data sheet pin information summary pin information summary ecp3-17ea ecp3-35ea ecp3-70e/ea pin type 256 ftbga 484 fpbga 256 ftbga 484 fpbga 672 fpbga 484 fpbga 672 fpbga 1156 fpbga general purpose inputs/outputs per bank bank 0 2636264248426086 bank 1 1424143636364878 bank 2 6 12 6 2424243436 bank 3 1844165459545986 bank 6 2044186361636786 bank 7 1932193642364854 bank 8 2424242424242424 general purpose inputs per bank bank 0 00000000 bank 1 00000000 bank 2 22244488 bank 3 0024441212 bank 6 0024441212 bank 7 44444488 bank 8 00000000 general purpose outputs per bank bank 0 00000000 bank 1 00000000 bank 2 00000000 bank 3 00000000 bank 6 00000000 bank 7 00000000 bank 8 00000000 total single-ended user i/o 133 222 133 295 310 295 380 490 vcc 6 16 6 1632163232 vccaux 48481281216 vtt 44444448 vcca 444484816 vccpll 24244444 vccio bank 0 22224244 bank 1 22224244 bank 2 22224244 bank 3 22224244 bank 6 22224244 bank 7 22224244 bank 8 22222222 vccj 11111111 tap 44444444 gnd, gndio 50 98 50 98 139 98 139 233 nc 0730 0960 0238 reserved 1 02022222 serdes 2626262626265278 miscellaneous pins 88888888 total bonded pins 256 484 256 484 672 484 672 1156
4-6 pinout information lattice semiconductor latticee cp3 family data sheet pin information summary (cont.) pin information summary ecp3-17ea ecp3-35ea pin type 256 ftbga 484 fpbga 256 ftbga 484 fpbga 672 fpbga emulated differential i/o per bank bank 0 1318132124 bank 1 7 12 7 18 18 bank 2 24188 bank 3 4 13 5 20 19 bank 6 5 13 6 22 20 bank 7 6 10 6 11 13 bank 8 1212121212 highspeed differential i/o per bank bank 0 00000 bank 1 00000 bank 2 23366 bank 3 594912 bank 6 5 9 4 11 12 bank 7 585910 bank 8 00000 total single ended/ total differential i/o per bank bank 0 26/13 36/18 26/13 42/21 48/24 bank 1 14/7 24/12 14/7 36/18 36/18 bank 2 8/4 14/7 8/4 28/14 28/14 bank 3 18/9 44/22 18/9 58/29 63/31 bank 6 20/10 44/22 20/10 67/33 65/32 bank 7 23/11 36/18 23/11 40/20 46/23 bank 8 24/12 24/12 24/12 24/12 24/12 ddr groups bonded per bank bank 0 23234 bank 1 12133 bank 2 01022 bank 3 13134 bank 6 13144 bank 7 12133 configuration bank 800000 serdes quads 11111 1. these pins must remain floating on the board.
4-7 pinout information lattice semiconductor latticee cp3 family data sheet pin information summary (cont.) pin information summary ecp3-70e ecp3-70ea pin type 484 fpbga 672 fpbga 1156 fpbga 484 fpbga 672 fpbga 1156 fpbga emulated differential ? i/o per bank bank 0 213043213043 bank 1 182439182439 bank 2 101516 8 1213 bank 3 232739202333 bank 6 263039222533 bank 7 142022111618 bank 8 121212121212 high-speed differential i/o per bank bank 0 000000 bank 1 000000 bank 2 466699 bank 3 6 81091216 bank 6 7 9 10111416 bank 7 68991213 bank 8 000000 total single-ended/ total differential i/o ? per bank bank 0 42/21 60/30 86/43 42/21 60/30 86/43 bank 1 36/18 48/24 78/39 36/18 48/24 78/39 bank 2 28/14 42/21 44/22 28/14 42/21 44/22 bank 3 58/29 71/35 98/49 58/29 71/35 98/49 bank 6 67/33 79/38 98/49 67/33 78/39 98/49 bank 7 40/20 56/28 62/31 40/20 56/28 62/31 bank 8 24/12 24/12 24/12 24/12 24/12 24/12 ddr groups bonded per bank bank 0 357357 bank 1 347347 bank 2 233233 bank 3 345345 bank 6 445445 bank 7 344344 configuration bank 8000000 serdes quads 123123
4-8 pinout information lattice semiconductor latticee cp3 family data sheet pin information summary (cont.) pin information summary ecp3-95e/ea ecp3-150ea pin type 484 fpbga 672 fpbga 1156 fpbga 672 fpbga 1156 fpbga general purpose inputs/outputs per bank bank 0 4260866094 bank 1 3648784886 bank 2 2434363458 bank 3 54598659104 bank 6 63678667104 bank 7 3648544876 bank 8 2424242424 general purpose inputs per bank bank 0 00000 bank 1 00000 bank 2 48888 bank 3 4 12 12 12 12 bank 6 4 12 12 12 12 bank 7 48888 bank 8 00000 general purpose outputs per bank bank 0 00000 bank 1 00000 bank 2 00000 bank 3 00000 bank 6 00000 bank 7 00000 bank 8 00000 total single-ended user i/o 295 380 490 380 586 vcc 1632323232 vccaux 8 12161216 vtt 44848 vcca 4 8 16 8 16 vccpll 44444 vccio bank 0 24444 bank 1 24444 bank 2 24444 bank 3 24444 bank 6 24444 bank 7 24444 bank 8 22222 vccj 11111 tap 44444 gnd, gndio 98 139 233 139 233 nc 0 0 238 0 116 reserved 1 22222 serdes 26527852104 miscellaneous pins 88888 total bonded pins 484 672 1156 672 1156
4-9 pinout information lattice semiconductor latticee cp3 family data sheet pin information summary (cont.) pin information summary ec p3-95e ecp3-95ea ecp3-150ea pin type 484 fpbga 672 fpbga 1156 fpbga 484 fpbga 672 fpbga 1156 fpbga 672 fpbga 1156 fpbga emulated differential i/o ? per bank bank 0 213043 21 30 43 3047 bank 1 182439 18 24 39 2443 bank 2 10 15 16 8 12 13 12 18 bank 3 232739 20 23 33 2337 bank 6 263039 22 25 33 2537 bank 7 142022 11 16 18 1624 bank 8 121212 12 12 12 1212 highspeed differential i/o ? per bank bank 0 000 0 0 0 00 bank 1 000 0 0 0 00 bank 2 4 6 6 6 9 9 9 15 bank 3 6 8 10 9 12 16 12 21 bank 6 79101114161421 bank 7 689 9 12131218 bank 8 000 0 0 0 00 total single ended/ total differential i/o per bank bank 0 42/21 60/30 86/43 42/21 60/30 86/43 60/30 94/47 bank 1 36/18 48/24 78/39 36/18 48/24 78/39 48/24 86/43 bank 2 28/14 42/21 44/22 28/14 42/21 44/22 42/21 66/33 bank 3 58/29 71/35 98/49 58/ 29 71/35 98/49 71/35 116/58 bank 6 67/33 78/39 98/49 67/ 33 78/39 98/49 78/39 116/58 bank 7 40/20 56/28 62/31 40/20 56/28 62/31 56/28 84/42 bank 8 24/12 24/12 24/12 24/12 24/12 24/12 24/12 24/12 ddr groups bonded ? per bank bank 0 357 3 5 7 57 bank 1 347 3 4 7 47 bank 2 233 2 3 3 34 bank 3 345 3 4 5 47 bank 6 445 4 4 5 47 bank 7 344 3 4 4 46 configuration bank8 000 0 0 0 00 serdes quads 1 2 3 1 2 3 2 4 1.these pins must remain floating on the board.
4-10 pinout information lattice semiconductor latticee cp3 family data sheet logic signal connections package pinout information can be found under ?data sheets? on the latticeecp3 product pages on the lattice website at www.latticesemi.com/products/fpga/ecp3 and in the lattice isplever de sign planner software. to cre- ate pinout information from within design planner, select view -> package view . then select select file -> export and choose a type of output file. see design planner help for more information. thermal management thermal management is recommended as part of any sound fpga design methodology. to assess the thermal characteristics of a system, lattice sp ecifies a maximum allowable junction temperature in all device data sheets. designers must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. refer to the thermal management document to find the device/package specific thermal values. for further information for further information regarding ther mal management, refer to the following: ? thermal management document ? tn1181, power consumption and management for latticeecp3 devices ? power calculator tool included wit h the lattice isplever design tool, or as a standalone download from ? www.latticesemi.com/software
www.latticesemi.com 5-1 ds1021 order info_01.2 march 2010 preliminary data sheet ds1021 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. latticeecp3 part number description lfe3 ? xxx xx ? x xxxxxx x grade c = commercial i = industrial logic capacity 17 = 17k luts 35 = 33k luts 70 = 67k luts 95 = 92k luts 150 = 149k luts supply voltage e or ea = 1.2v speed 6 = slowest 7 8 = fastest package ftn256 = 256-ball lead-free ftbga fn484 = 484-ball lead-free fpbga fn672 = 672-ball lead-free fpbga fn1156 = 1156-ball lead-free fpbga device family ecp3 (latticeecp3 fpga + serdes) ordering information latticeecp3 devices have top-side markings, for co mmercial and industrial grades, as shown below: lfe3-95e 7fn672c datecode ecp3 lfe3-95e 7fn672i datecode commercial industrial ecp3 latticeecp3 family data sheet ordering information
5-2 ordering information lattice semiconductor latticee cp3 family data sheet latticeecp3 devices, lead-free packaging the following devices may have associated errata. specific devices with associated errata will be notated with a footnote. commercial part number voltage grade package pins temp. luts (k) lfe3-17ea-6ftn256c 1.2v -6 lead-free ftbga 256 com 17 lfe3-17ea-7ftn256c 1.2v -7 lead-free ftbga 256 com 17 lfe3-17ea-8ftn256c 1.2v -8 lead-free ftbga 256 com 17 lfe3-17ea-6fn484c 1.2v -6 lead-free fpbga 484 com 17 lfe3-17ea-7fn484c 1.2v -7 lead-free fpbga 484 com 17 lfe3-17ea-8fn484c 1.2v -8 lead-free fpbga 484 com 17 part number voltage grade package pins temp. luts (k) lfe3-35ea-6ftn256c 1.2v -6 lead-free ftbga 256 com 33 lfe3-35ea-7ftn256c 1.2v -7 lead-free ftbga 256 com 33 lfe3-35ea-8ftn256c 1.2v -8 lead-free ftbga 256 com 33 lfe3-35ea-6fn484c 1.2v -6 lead-free fpbga 484 com 33 lfe3-35ea-7fn484c 1.2v -7 lead-free fpbga 484 com 33 lfe3-35ea-8fn484c 1.2v -8 lead-free fpbga 484 com 33 lfe3-35ea-6fn672c 1.2v -6 lead-free fpbga 672 com 33 lfe3-35ea-7fn672c 1.2v -7 lead-free fpbga 672 com 33 lfe3-35ea-8fn672c 1.2v -8 lead-free fpbga 672 com 33 part number voltage grade package pins temp. luts (k) lfe3-70ea-6fn484c 1.2v -6 lead-free fpbga 484 com 67 lfe3-70ea-7fn484c 1.2v -7 lead-free fpbga 484 com 67 lfe3-70ea-8fn484c 1.2v -8 lead-free fpbga 484 com 67 lfe3-70ea-6fn672c 1.2v -6 lead-free fpbga 672 com 67 lfe3-70ea-7fn672c 1.2v -7 lead-free fpbga 672 com 67 lfe3-70ea-8fn672c 1.2v -8 lead-free fpbga 672 com 67 lfe3-70ea-6fn1156c 1.2v -6 lead-free fpbga 1156 com 67 lfe3-70ea-7fn1156c 1.2v -7 lead-free fpbga 1156 com 67 lfe3-70ea-8fn1156c 1.2v -8 lead-free fpbga 1156 com 67
5-3 ordering information lattice semiconductor latticee cp3 family data sheet part number voltage grade package pins temp. luts (k) lfe3-70e-6fn484c 1 1.2v -6 lead-free fpbga 484 com 67 lfe3-70e-7fn484c 1 1.2v -7 lead-free fpbga 484 com 67 lfe3-70e-8fn484c 1 1.2v -8 lead-free fpbga 484 com 67 lfe3-70e-6fn672c 1 1.2v -6 lead-free fpbga 672 com 67 lfe3-70e-7fn672c 1 1.2v -7 lead-free fpbga 672 com 67 lfe3-70e-8fn672c 1 1.2v -8 lead-free fpbga 672 com 67 lfe3-70e-6fn1156c 1 1.2v -6 lead-free fpbga 1156 com 67 lfe3-70e-7fn1156c 1 1.2v -7 lead-free fpbga 1156 com 67 lfe3-70e-8fn1156c 1 1.2v -8 lead-free fpbga 1156 com 67 1.this device has associated errata. view www.latticesemi.com/documents/ds1021.zip for a description of the errata. part number voltage grade package pins temp. luts (k) lfe3-95ea-6fn484c 1.2v -6 lead-free fpbga 484 com 92 lfe3-95ea-7fn484c 1.2v -7 lead-free fpbga 484 com 92 lfe3-95ea-8fn484c 1.2v -8 lead-free fpbga 484 com 92 LFE3-95EA-6FN672C 1.2v -6 lead-free fpbga 672 com 92 lfe3-95ea-7fn672c 1.2v -7 lead-free fpbga 672 com 92 lfe3-95ea-8fn672c 1.2v -8 lead-free fpbga 672 com 92 lfe3-95ea-6fn1156c 1.2v -6 lead-free fpbga 1156 com 92 lfe3-95ea-7fn1156c 1.2v -7 lead-free fpbga 1156 com 92 lfe3-95ea-8fn1156c 1.2v -8 lead-free fpbga 1156 com 92 part number voltage grade package pins temp. luts (k) lfe3-95e-6fn484c 1 1.2v -6 lead-free fpbga 484 com 92 lfe3-95e-7fn484c 1 1.2v -7 lead-free fpbga 484 com 92 lfe3-95e-8fn484c 1 1.2v -8 lead-free fpbga 484 com 92 lfe3-95e-6fn672c 1 1.2v -6 lead-free fpbga 672 com 92 lfe3-95e-7fn672c 1 1.2v -7 lead-free fpbga 672 com 92 lfe3-95e-8fn672c 1 1.2v -8 lead-free fpbga 672 com 92 lfe3-95e-6fn1156c 1 1.2v -6 lead-free fpbga 1156 com 92 lfe3-95e-7fn1156c 1 1.2v -7 lead-free fpbga 1156 com 92 lfe3-95e-8fn1156c 1 1.2v -8 lead-free fpbga 1156 com 92 1.this device has associated errata. view www.latticesemi.com/documents/ds1021.zip for a description of the errata. part number voltage grade package pins temp. luts (k) lfe3-150ea-6fn672c 1.2v -6 lead-free fpbga 672 com 149 lfe3-150ea-7fn672c 1.2v -7 lead-free fpbga 672 com 149 lfe3-150ea-8fn672c 1.2v -8 lead-free fpbga 672 com 149 lfe3-150ea-6fn1156c 1.2v -6 lead-free fpbga 1156 com 149 lfe3-150ea-7fn1156c 1.2v -7 lead-free fpbga 1156 com 149 lfe3-150ea-8fn1156c 1.2v -8 lead-free fpbga 1156 com 149
5-4 ordering information lattice semiconductor latticee cp3 family data sheet part number voltage grade package pins temp. luts (k) lfe3-150ea-6fn672ctw* 1.2v -6 lead-free fpbga 672 com 149 lfe3-150ea-7fn672ctw* 1.2v -7 lead-free fpbga 672 com 149 lfe3-150ea-8fn672ctw* 1.2v -8 lead-free fpbga 672 com 149 lfe3-150ea-6fn1156ctw* 1.2v -6 lead-free fpbga 1156 com 149 lfe3-150ea-7fn1156ctw* 1.2v -7 lead-free fpbga 1156 com 149 lfe3-150ea-8fn1156ctw* 1.2v -8 lead-free fpbga 1156 com 149 *note: specifications for the lfe3-150ea- sp fn pkg ctw and lfe3-150ea- sp fn pkg itw devices, (where sp is the speed and pkg is the package), are the same as the lfe3-150ea- sp fn pkg c and lfe3-150ea- sp fn pkg i devices respectively, except as specified below. ? the ctc (clock tolerance circuit) inside the serdes hard pcs in the tw device is not functional but it can be bypassed and implemented in soft ip. ? the serdes xres pin on the tw device passes cdm testing at 250v.
5-5 ordering information lattice semiconductor latticee cp3 family data sheet industrial the following devices may have associated errata. specific devices with associated errata will be notated with a footnote. part number voltage grade package pins temp. luts (k) lfe3-17ea-6ftn256i 1.2v -6 lead-free ftbga 256 ind 17 lfe3-17ea-7ftn256i 1.2v -7 lead-free ftbga 256 ind 17 lfe3-17ea-8ftn256i 1.2v -8 lead-free ftbga 256 ind 17 lfe3-17ea-6fn484i 1.2v -6 lead-free fpbga 484 ind 17 lfe3-17ea-7fn484i 1.2v -7 lead-free fpbga 484 ind 17 lfe3-17ea-8fn484i 1.2v -8 lead-free fpbga 484 ind 17 part number voltage grade package pins temp. luts (k) lfe3-35ea-6ftn256i 1.2v -6 lead-free ftbga 256 ind 33 lfe3-35ea-7ftn256i 1.2v -7 lead-free ftbga 256 ind 33 lfe3-35ea-8ftn256i 1.2v -8 lead-free ftbga 256 ind 33 lfe3-35ea-6fn484i 1.2v -6 lead-free fpbga 484 ind 33 lfe3-35ea-7fn484i 1.2v -7 lead-free fpbga 484 ind 33 lfe3-35ea-8fn484i 1.2v -8 lead-free fpbga 484 ind 33 lfe3-35ea-6fn672i 1.2v -6 lead-free fpbga 672 ind 33 lfe3-35ea-7fn672i 1.2v -7 lead-free fpbga 672 ind 33 lfe3-35ea-8fn672i 1.2v -7 lead-free fpbga 672 ind 33 part number voltage grade package pins temp. luts (k) lfe3-70ea-6fn484i 1.2v -6 lead-free fpbga 484 ind 67 lfe3-70ea-7fn484i 1.2v -7 lead-free fpbga 484 ind 67 lfe3-70ea-8fn484i 1.2v -8 lead-free fpbga 484 ind 67 lfe3-70ea-6fn672i 1.2v -6 lead-free fpbga 672 ind 67 lfe3-70ea-7fn672i 1.2v -7 lead-free fpbga 672 ind 67 lfe3-70ea-8fn672i 1.2v -8 lead-free fpbga 672 ind 67 lfe3-70ea-6fn1156i 1.2v -6 lead-free fpbga 1156 ind 67 lfe3-70ea-7fn1156i 1.2v -7 lead-free fpbga 1156 ind 67 lfe3-70ea-8fn1156i 1.2v -8 lead-free fpbga 1156 ind 67
5-6 ordering information lattice semiconductor latticee cp3 family data sheet part number voltage grade package pins temp. luts (k) lfe3-70e-6fn484i 1 1.2v -6 lead-free fpbga 484 ind 67 lfe3-70e-7fn484i 1 1.2v -7 lead-free fpbga 484 ind 67 lfe3-70e-8fn484i 1 1.2v -8 lead-free fpbga 484 ind 67 lfe3-70e-6fn672i 1 1.2v -6 lead-free fpbga 672 ind 67 lfe3-70e-7fn672i 1 1.2v -7 lead-free fpbga 672 ind 67 lfe3-70e-8fn672i 1 1.2v -8 lead-free fpbga 672 ind 67 lfe3-70e-6fn1156i 1 1.2v -6 lead-free fpbga 1156 ind 67 lfe3-70e-7fn1156i 1 1.2v -7 lead-free fpbga 1156 ind 67 lfe3-70e-8fn1156i 1 1.2v -8 lead-free fpbga 1156 ind 67 1.this device has associated errata. view www.latticesemi.com/documents/ds1021.zip for a description of the errata. part number voltage grade package pins temp. luts (k) lfe3-95ea-6fn484i 1.2v -6 lead-free fpbga 484 ind 92 lfe3-95ea-7fn484i 1.2v -7 lead-free fpbga 484 ind 92 lfe3-95ea-8fn484i 1.2v -8 lead-free fpbga 484 ind 92 lfe3-95ea-6fn672i 1.2v -6 lead-free fpbga 672 ind 92 lfe3-95ea-7fn672i 1.2v -7 lead-free fpbga 672 ind 92 lfe3-95ea-8fn672i 1.2v -8 lead-free fpbga 672 ind 92 lfe3-95ea-6fn1156i 1.2v -6 lead-free fpbga 1156 ind 92 lfe3-95ea-7fn1156i 1.2v -7 lead-free fpbga 1156 ind 92 lfe3-95ea-8fn1156i 1.2v -8 lead-free fpbga 1156 ind 92 part number voltage grade package pins temp. luts (k) lfe3-95e-6fn484i 1 1.2v -6 lead-free fpbga 484 ind 92 lfe3-95e-7fn484i 1 1.2v -7 lead-free fpbga 484 ind 92 lfe3-95e-8fn484i 1 1.2v -8 lead-free fpbga 484 ind 92 lfe3-95e-6fn672i 1 1.2v -6 lead-free fpbga 672 ind 92 lfe3-95e-7fn672i 1 1.2v -7 lead-free fpbga 672 ind 92 lfe3-95e-8fn672i 1 1.2v -8 lead-free fpbga 672 ind 92 lfe3-95e-6fn1156i 1 1.2v -6 lead-free fpbga 1156 ind 92 lfe3-95e-7fn1156i 1 1.2v -7 lead-free fpbga 1156 ind 92 lfe3-95e-8fn1156i 1 1.2v -8 lead-free fpbga 1156 ind 92 1.this device has associated errata. view www.latticesemi.com/documents/ds1021.zip for a description of the errata.
5-7 ordering information lattice semiconductor latticee cp3 family data sheet part number voltage grade package pins temp. luts (k) lfe3-150ea-6fn672i 1.2v -6 lead-free fpbga 672 ind 149 lfe3-150ea-7fn672i 1.2v -7 lead-free fpbga 672 ind 149 lfe3-150ea-8fn672i 1.2v -8 lead-free fpbga 672 ind 149 lfe3-150ea-6fn1156i 1.2v -6 lead-free fpbga 1156 ind 149 lfe3-150ea-7fn1156i 1.2v -7 lead-free fpbga 1156 ind 149 lfe3-150ea-8fn1156i 1.2v -8 lead-free fpbga 1156 ind 149 part number voltage grade package pins temp. luts (k) lfe3-150ea-6fn672itw* 1.2v -6 lead-free fpbga 672 ind 149 lfe3-150ea-7fn672itw* 1.2v -7 lead-free fpbga 672 ind 149 lfe3-150ea-8fn672itw* 1.2v -8 lead-free fpbga 672 ind 149 lfe3-150ea-6fn1156itw* 1.2v -6 lead-free fpbga 1156 ind 149 lfe3-150ea-7fn1156itw* 1.2v -7 lead-free fpbga 1156 ind 149 lfe3-150ea-8fn1156itw* 1.2v -8 lead-free fpbga 1156 ind 149 *note: specifications for the lfe3-150ea- sp fn pkg ctw and lfe3-150ea- sp fn pkg itw devices, (where sp is the speed and pkg is the package), are the same as the lfe3-150ea- sp fn pkg c and lfe3-150ea- sp fn pkg i devices respectively, except as specified below. ? the ctc (clock tolerance circuit) inside the serdes hard pcs in the tw device is not functional but it can be bypassed and implemented in soft ip. ? the serdes xres pin on the tw device passes cdm testing at 250v.
february 2009 preliminary data sheet ds1021 ? 2009 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. www.latticesemi.com 6-1 ds1021 further info_01.0 for further information a variety of technical notes for the latticeecp3 family are available on the lattice website at www.latticesemi.com . ? tn1169, latticeecp3 sysconfig usage guide ? tn1176, latticeecp3 serdes/pcs usage guide ? tn1177, latticeecp3 sysio usage guide ? tn1178, latticeecp3 sysclock pll/dll design and usage guide ? tn1179, latticeecp3 memory usage guide ? tn1180, latticeecp3 high-speed i/o interface ? tn1181, power consumption and management for latticeecp3 devices ? tn1182, latticeecp3 sysdsp usage guide ? tn1184, latticeecp3 soft error dete ction (sed) usage guide ? tn1189, latticeecp3 hardware checklist for further information on interface standards refer to the following websites: ? jedec standards (lvttl , lvcmos, sstl, hstl): www.jedec.org ?pci: www.pcisig.com latticeecp3 family data sheet supplemental information
march 2010 preliminary data sheet ds1021 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. www.latticesemi.com 7-1 ds1021 revision history date version section change summary february 2009 01.0 ? initial release. may 2009 01.1 all removed references to parallel burst mode flash. introduction features - changed 250 mbps to 230 mbps in embedded serdes bul- leted section and added a footnote to indicate 230 mbps applies to 8b10b and 10b12b applications. updated data for ecp3-17 in latticeecp3 family selection guide table. changed embedded memory from 552 to 700 kbits in latticeecp3 family selection guide table. architecture updated description for clkfb in general purpose pll diagram. corrected primary clock sources text section. corrected secondary clock/con trol sources text section. corrected secondary clock regions table. corrected note below detailed sysdsp slice diagram. corrected clock, clock enable, and reset resources text section. corrected ecp3-17 ebr number in embedded sram in the latticeecp3 family table. added on-chip termination options for input modes table. updated available serdes quads per latticeecp3 devices table. updated simplified channel block diagram for serdes/pcs block diagram. updated device configuration text section. corrected software default value of mclk to be 2.5 mhz. dc and switching characteristics updated vccob min/max data in re commended operating conditions table. corrected footnote 2 in sysio recommended operating conditions table. added added footnote 7 for t skew_prib to external switching charac- teristics table. added 2-to-1 gearing text section and table. updated external reference clock sp ecification (refclkp/refclkn) table. latticeecp3 sysconfig port timing specifications - updated t dinit information. added sysconfig port timing waveform. serial input data specifications table, delete typ data for v rx-diff-s . added footnote 4 to sysclock pll timing table for t pfd . added serdes/pcs block latency breakdown table. external reference clock specifications table, added footnote 4, add symbol name vref-in-diff. added serdes external reference clock waveforms. updated serial output timing and levels table. pin-to-pin performance table, changed "t ypically 3% slower" to "typically slower". latticeecp3 family data sheet revision history
7-2 revision history lattice semiconductor latticee cp3 family data sheet may 2009 (cont.) 01.1 (cont.) dc and switching characteristics (cont.) updated timing information updated serdes minimum frequency. added data to the following tables: external switching characteristics, internal switching characteristics, family timing adders, maximum i/o buffer speed, dll timing, high speed data transmitter, channel out- put jitter, typical building block function performance, register-to- register performance, and power supply requirements. updated serial input data specifications table. updated transmit table, serial rapid i/o type 2 electrical and timing characteristics section. pinout information updated signal description tables. updated pin information summar y tables and added footnote 1. july 2009 01.2 multiple changed references of ?mul ti-boot? to ?dual-boot? throughout the data sheet. architecture updated on-chip programmable termination bullets. updated on-chip termination options for input modes table. updated on-chip termination figure. dc and switching characterisitcs changed min/max data for fref_ppm and added footnote 4 in serdes external reference clock specification table. updated serdes minimum frequency. pinout information corrected mclk to be i/o and cclk to be i in signal descriptions table august 2009 01.3 dc and switching characterisitcs corrected truncated numbers for v ccib and v ccob in recommended operating conditions table. september 2009 01.4 architect ure corrected link in sysmem memory block section. updated information for on-chip programmable termination and modi- fied corresponding figure. added footnote 2 to on-chip programmable termination options for input modes table. corrected per quadrant primary clock selection figure. dc and switching characterisitcs modified -8 timing data for 1024x18 true-dual port ram (read-before- write, ebr output registers) added esd performance table. latticeecp3 external switching characteristics table - updated data for t dibgddr , t w_pri , t w_edge and t skew_edge_dqs . latticeecp3 internal switching characteristics table - updated data for t coo_pio and added footnote #4. sysclock pll timing table - updated data for f out . external reference clock specificat ion (refclkp/refclkn) table - updated data for v ref-in-se and v ref-in-diff . latticeecp3 sysconfig port timing specifications table - updated data for t mwc . added trlvds dc specification table and diagram. updated mini lvds table. november 2009 01.5 introduction updated embedded serdes features. added sonet/sdh to embed ded serdes protocols. architecture updated figure 2-4, general purpose pll diagram. updated sonet/sdh to se rdes and pcs protocols. date version section change summary
7-3 revision history lattice semiconductor latticee cp3 family data sheet november 2009 (cont.) 01.5 (cont.) architecture (cont.) updated table 2-13, serdes standard support to include sonet/ sdh and updated footnote 2. dc and switching characterisitcs added footnote to esd performance table. updated serdes power supply re quirements table and footnotes. updated maximum i/o buffer speed table. updated pin-to-pin peformance table. updated sysclock pll timing table. updated dll timing table. updated high-speed data transmitter tables. updated high-speed data receiver table. updated footnote for receiver total jitter tolerance specification table. updated periodic receiver jitter tolerance specification table. updated serdes external reference clock specification table. updated pci express electrical and timing ac and dc characteristics. deleted reference clock table for pci express electrical and timing ac and dc characteristics. updated smpte ac/dc characteristics transmit table. updated mini lvds table. updated rsds table. added supply current (standby) table for ea devices. updated internal switching characteristics table. updated register-to-register performance table. added hdmi electrical and timing characteristics data. updated family timing adders table. updated sysconfig port timing specifications table. updated recommended operating conditions table. updated hot socket specifications table. updated single-ended dc table. updated trlvds table and figure. updated serial data input specifications table. updated hdmi transmit and receive table. ordering information added lfe3-150ea ?tw? de vices and footnotes to the commercial and industrial tables. march 2010 01.6 architecture added read-before-write information. dc and switching characteristics added footnote #6 to maximum i/o buffer speed table. corrected minimum operating conditions for input and output differential voltages in the point-to-point lvds table. pinout information added pin information fo r the latticeecp3-70ea and latticeecp3- 95ea devices. ordering information added ordering part numbers for the latticeecp3-70ea and latticeecp3-95ea devices. removed dual mark information. date version section change summary

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